The core components of MLRISC allow the client to quickly construct
an optimizing backend for various architectures. These components include:
The MLTREE language, which is a RTL-like intermediate language
that is used to communicate to the MLRISC system. A client is
responsible for writing the translator that generates MLTREE from
the source program.
Instruction selection modules, which generates target machine
instructions from the MLTREE intermediate language.
The Register Allocator, which performs register allocation.
Assemblers, which emits assembly code.
For systems that require direct machine code generation, the following
modules are included:
Span dependency resolution modules, which compute addresses
frmo symbolic addresses,
fill delay slots, and expand instructions that are
Machine code emitters, which emit machine code into a binary stream.
In addition, MLRISC has been enhanced to support various types of
machine level optimizations. These include:
Core optimizations, which various types of control flow transformation
Annotations -- this is
a generic mechinism for propagating information in the MLRISC sstem.
The client may attach arbitrary annotation of various granularity
to MLRISC's program representation,
which can then be propagated to later phases.
These can be information related to profiling frequency, dependence,
comments, and/or types.
The same mechanism is also used to propagate
analysis information one optimization phase to
Instruction Streams -- an abstraction
for describing a stream of instructions. Instruction streams are
used to connect modules such as instruction selection, assembler,
machine code emitter, and
control flow graph builder.
Regmap -- a mapping between registers
names. MLRISC register allocators represent the result of register
allocation as a regmap.
Conversion modules between the two representations are provided.
In general MLRISC optimization phases are transformations applied on one
of these representations. Optimizations may be chained together to form
a compiler backend. For example, a minimal backend consists of
the instruction selection module, which translates
MLTree into target instructions,
the flowgraph builder, which conversts a stream of target instructions
into a cluster,
the register allocator, which performs register allocation, and
the assembly code emitter, which generates assembly output