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[smlnj] Diff of /MLRISC/releases/release-110.60/instructions/cells.sig
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Diff of /MLRISC/releases/release-110.60/instructions/cells.sig

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revision 245, Sat Apr 17 18:47:12 1999 UTC revision 411, Fri Sep 3 00:25:03 1999 UTC
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1  (* cells.sig  (*
2     * Description of registers and other updatable cells.
3     *
4     * IMPORTANT NOTE:
5     * All physical registers in the machine architecture
6     * all given unique encodings.  The encoding is not necessarily zero based.
7     * For example, 0 may NOT represent floating point register 0.
8     *
9     * This means that the client should not
10     * use hard coded integers to represent physical registers,
11     * but should instead use the function:
12     *
13     *    Reg : cellkind -> int -> register
14   *   *
15   * COPYRIGHT (c) 1995 AT&T Bell Laboratories.   * to compute the proper encoding.
16   *   *
17   * CELLS - describes storage units on the machine, such as   * A call "Reg k n" returns the nth physical register of kind k.
18   *         dedicated and general registers, memory ...   * For integer and float point registers, the functions:
19   *   *
20   *       This file acts as a bridge between MLRISC and the machine   *   GPReg : int -> register
21   *       code.   *   FPReg : int -> register
22   *   *
23     * can also be used as shortcuts.
24     *
25     * -- Allen.
26   *)   *)
27  signature CELLS = sig  signature CELLS_BASIS =
28    sig
29       eqtype cellkind
30    type register = int    type register = int
31    type regmap = register Intmap.intmap    type regmap = register Intmap.intmap
   eqtype cellclass  
32    exception Cells    exception Cells
   val GP   : cellclass  (* general purpose register *)  
   val FP   : cellclass  (* floating point register *)  
   val CC   : cellclass  (* conditional code register *)  
   val MEM  : cellclass  (* memory *)  
   val CTRL : cellclass  (* control dependence *)  
   
   val stackptrR : int                   (* stack pointer register *)  
   val asmTmpR : int                     (* assembly temporary *)  
   val fasmTmp : int                     (* floating point temporary *)  
   
   val newCell : cellclass -> unit -> register (* generate a new name *)  
   val numCell : cellclass -> unit -> int (* number of names in class *)  
   val maxCell : unit -> int              (* max id of name *)  
   val cellToString : register * cellclass -> string  
   
   val newReg : unit -> register         (* newClass GP *)  
   val newFreg : unit -> register        (* newClass FP *)  
   val newCCreg : unit -> register       (* newClass CC *)  
33    
34       val cellkinds : cellkind list  (* list of all the cellkinds *)
35    
36       val cellkindToString : cellkind -> string
37    
38           (* first pseudo register *)
39    val firstPseudo : register    val firstPseudo : register
   val zero : cellclass -> register option  
        (* name of the register that contains zero *)  
40    
41    val resetRegs : unit -> regmap (* reset any local state *)         (* returns the encoding for the nth physical register of the given kind,
42            * raises Cells if there is none.
43            *)
44       val Reg   : cellkind -> int -> register
45       val GPReg : int -> register (* Reg GP *)
46       val FPReg : int -> register (* Reg FP *)
47    
48    type cellset         (* given a cellkind returns its encoding range *)
49    val cellset2string : cellset -> string     val cellRange : cellkind -> {low:int, high:int}
   val empty          : cellset  
   val addCell        : cellclass -> register * cellset -> cellset  
   val cellsetToRegs  : regmap * cellset -> register list  
50    
51    val addReg  : register * cellset -> cellset (* addCell GP *)         (* generate a new name for a virtual register *)
52    val addFreg : register * cellset -> cellset (* addCell FP *)     val newCell   : cellkind -> unit -> register
53  end  
54           (* lookup the cellkind of a virtual register *)
55       val cellKind : register -> cellkind
56    
57           (* update the cellkind of a virtual register *)
58       val updateCellKind : register * cellkind -> unit
59    
60           (* lookup the number of virtual registers in a cellkind *)
61       val numCell   : cellkind -> unit -> int
62    
63           (* the next virtual register name *)
64       val maxCell   : unit -> register
65    
66           (* newCell GP *)
67       val newReg    : unit -> register
68    
69           (* newCell FP *)
70       val newFreg   : unit -> register
71    
72           (* Create a new register that has the same cellkind as the given one
73            * Note: the numCell kind is NOT updated!
74            *)
75       val newVar    : register -> register
76    
77           (* create a new regmap *)
78       val regmap    : unit -> regmap
79       val lookup    : regmap -> register -> register
80    
81           (* reset all counters *)
82       val reset     : unit -> unit
83    
84            (* auxiliary functions *)
85       val printSet : (register -> string) -> (register list -> string)
86       val printTuple : string list * string list -> string
87    end
88    
89  (*  (*
90   * $Log: cells.sig,v $   * This is the abstract interface of cells
  * Revision 1.4  1998/10/06 14:07:45  george  
  * Flowgraph has been removed from modules that do not need it.  
  * Changes to compiler/CodeGen/*/*{MLTree,CG}.sml necessary.  
  *                                              [leunga]  
  *  
  * Revision 1.3  1998/05/25 15:11:02  george  
  *   Fixed RCS keywords  
  *  
91   *)   *)
92    signature CELLS =
93    sig
94       include CELLS_BASIS
95       val GP   : cellkind  (* general purpose *)
96       val FP   : cellkind  (* floating point *)
97       val CC   : cellkind  (* condition code *)
98       val MEM  : cellkind  (* memory cell *)
99       val CTRL : cellkind  (* control dependence *)
100       val toString : cellkind -> register -> string
101       val stackptrR : register                    (* stack pointer register *)
102       val asmTmpR : register                      (* assembly temporary *)
103       val fasmTmp : register                      (* floating point temporary *)
104       val zeroReg : cellkind -> register option   (* register that contains 0 *)
105    
106       type cellset
107    
108          (* building a cellset *)
109       val empty      : cellset
110       val addCell    : cellkind -> register * cellset -> cellset
111       val addReg     : register * cellset -> cellset
112       val addFreg    : register * cellset -> cellset
113       val getCell    : cellkind -> cellset -> register list
114       val updateCell : cellkind -> cellset * register list -> cellset
115    
116           (* pretty printing, the second one takes a regmap *)
117       val cellsetToString : cellset -> string
118       val cellsetToString' : (register -> register) -> cellset -> string
119    
120           (* convert cellset into a list of registers *)
121       val cellsetToRegs : cellset -> register list
122    end

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