Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Diff of /MLRISC/trunk/amd64/ra/amd64RegAlloc.sml
ViewVC logotype

Diff of /MLRISC/trunk/amd64/ra/amd64RegAlloc.sml

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 2928, Fri Jan 18 00:50:49 2008 UTC revision 2929, Fri Jan 18 20:40:28 2008 UTC
# Line 49  Line 49 
49            val phases    : ra_phase list            val phases    : ra_phase list
50        end        end
51    
52         (* guaranteeing that floats are stored at 16-byte aligned addresses reduces the number of instructions *)
53          val floats16ByteAligned : bool
54    
55      ) : CFG_OPTIMIZATION =      ) : CFG_OPTIMIZATION =
56    struct    struct
57    
# Line 159  Line 162 
162                         structure Asm = Asm)                         structure Asm = Asm)
163      structure SpillInstr = AMD64SpillInstr (      structure SpillInstr = AMD64SpillInstr (
164                 structure I = I                 structure I = I
165                 structure Props = Props)                 structure Props = Props
166                   val floats16ByteAligned = true)
167      val spillFInstr = SpillInstr.spill CB.FP      val spillFInstr = SpillInstr.spill CB.FP
168      val reloadFInstr = SpillInstr.reload CB.FP      val reloadFInstr = SpillInstr.reload CB.FP
169      val spillInstr = SpillInstr.spill CB.GP      val spillInstr = SpillInstr.spill CB.GP

Legend:
Removed from v.2928  
changed lines
  Added in v.2929

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0