Diff of /MLRISC/trunk/amd64/staged-allocation/amd64-svid-fn.sml

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	revision 3041, Wed May 28 18:39:35 2008 UTC	revision 3042, Wed May 28 23:40:21 2008 UTC
#	Line 81	Line 81
81	val cCallGpr = SA.freshCounter ()	val cCallGpr = SA.freshCounter ()
82	val cCallFpr = SA.freshCounter ()	val cCallFpr = SA.freshCounter ()
83	(* initial store *)	(* initial store *)
84
85	val str0 = SA.init [cCallStk, cCallGpr, cCallFpr, cRetFpr, cRetGpr]	val str0 = SA.init [cCallStk, cCallGpr, cCallFpr, cRetFpr, cRetGpr]
86
87	val callStages = [	val callStages = [
#	Line 104	Line 105
105
106	end  (* CCs *)	end  (* CCs *)
107
108		fun offSp 0 = CCs.spReg
109		| offSp offset = T.ADD (wordTy, CCs.spReg, T.LI offset)
110
111	structure CCall = CCallFn (	structure CCall = CCallFn (
112	structure T = T	structure T = T
113	structure C = C	structure C = C
114	val wordTy = wordTy	val wordTy = wordTy
115	fun offSp 0 = CCs.spReg	val offSp = offSp)
	| offSp offset = T.ADD (wordTy, CCs.spReg, T.LI offset))
116
117	datatype c_arg = datatype CCall.c_arg	datatype c_arg = datatype CCall.c_arg
118

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Legend: Removed from v.3041   changed lines   Added in v.3042

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