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[smlnj] Diff of /MLRISC/trunk/amd64/staged-allocation/test.sml
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Diff of /MLRISC/trunk/amd64/staged-allocation/test.sml

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revision 2993, Thu Apr 17 01:02:19 2008 UTC revision 3000, Tue Apr 22 08:01:00 2008 UTC
# Line 200  Line 200 
200          end          end
201      fun spillInit _ = ()      fun spillInit _ = ()
202      fun spillLoc {info=frame, an, cell, id=loc} =      fun spillLoc {info=frame, an, cell, id=loc} =
203          {opnd = AMD64Instr.Immed 0, kind = SPILL_LOC}  raise Fail ""
204    (*        {opnd = AMD64Instr.Immed 0, kind = SPILL_LOC}*)
205      val phases = [SPILL_PROPAGATION, SPILL_COLORING]      val phases = [SPILL_PROPAGATION, SPILL_COLORING]
206    end (* IntRA *)    end (* IntRA *)
207    
# Line 209  Line 210 
210      val avail = C.Regs CellsBasis.FP {from=0, to=15, step=1}      val avail = C.Regs CellsBasis.FP {from=0, to=15, step=1}
211      val dedicated = []      val dedicated = []
212      fun spillInit _ = ()      fun spillInit _ = ()
213      fun spillLoc (info, ans, id) = AMD64Instr.Immed 0      fun spillLoc (info, ans, id) = raise Fail ""
214      val phases = [SPILL_PROPAGATION, SPILL_COLORING]      val phases = [SPILL_PROPAGATION, SPILL_COLORING]
215    end (* FloatRA *)    end (* FloatRA *)
216    
# Line 236  Line 237 
237  structure CCalls = AMD64SVID (  structure CCalls = AMD64SVID (
238             structure T = AMD64MLTree             structure T = AMD64MLTree
239             val frameAlign = 16)             val frameAlign = 16)
240    
241    
242    structure RA2 =
243        RISC_RA
244        (structure I = AMD64Instr
245         structure Asm = AMD64Asm
246         structure CFG = AMD64CFG
247         structure InsnProps = AMD64InsnProps
248         structure Rewrite =
249           struct
250             structure I = AMD64Instr
251             fun rewriteDef _ = raise Fail ""
252             fun rewriteUse _ = raise Fail ""
253             fun frewriteDef _ = raise Fail ""
254             fun frewriteUse _ = raise Fail ""
255           end
256         structure SpillInstr = AMD64SpillInstr (
257                   structure I = I
258                   structure Props = AMD64InsnProps
259                   val floats16ByteAligned = true)
260         structure SpillHeur = ChaitinSpillHeur
261         structure Spill = RASpill (structure InsnProps = AMD64InsnProps
262                                    structure Asm = AMD64Asm)
263    
264         datatype spillOperandKind = SPILL_LOC | CONST_VAL
265         type spill_info = unit
266         fun beforeRA _ = raise Fail ""
267    
268         val architecture = "amd64"
269         fun pure _ = true
270    
271         structure Int =
272            struct
273              val avail = []
274              val dedicated = []
275              fun spillLoc _ = raise Fail ""
276              val mode = RACore.NO_OPTIMIZATION
277            end
278         structure Float =
279            struct
280              val avail = []
281              val dedicated = []
282              fun spillLoc _ = raise Fail ""
283              val mode = RACore.NO_OPTIMIZATION
284            end
285    
286        )
287    

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