Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Diff of /MLRISC/trunk/amd64/staged-allocation/test.sml
ViewVC logotype

Diff of /MLRISC/trunk/amd64/staged-allocation/test.sml

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 3042, Wed May 28 23:40:21 2008 UTC revision 3058, Tue Jun 3 17:17:28 2008 UTC
# Line 130  Line 130 
130  end (* AMD64PseudoOps *)  end (* AMD64PseudoOps *)
131  *)  *)
132    
133  (*  
134  functor AMD64PseudoOpsFn (  functor AMD64PseudoOpsFn (
135      structure T : MLTREE      structure T : MLTREE
136      structure MLTreeEval : MLTREE_EVAL where T = T      structure MLTreeEval : MLTREE_EVAL where T = T
137    ) : PSEUDO_OPS_BASIS = AMD64GasPseudoOps (    ) : PSEUDO_OPS_BASIS = AMD64GasPseudoOps (
138      structure T = T      structure T = T
139      structure MLTreeEval = MLTreeEval)      structure MLTreeEval = MLTreeEval)
 *)  
140    
141    (*
142  functor AMD64PseudoOpsFn (  functor AMD64PseudoOpsFn (
143      structure T : MLTREE      structure T : MLTREE
144      structure MLTreeEval : MLTREE_EVAL where T = T      structure MLTreeEval : MLTREE_EVAL where T = T
145    ) : PSEUDO_OPS_BASIS = AMD64DarwinPseudoOps (    ) : PSEUDO_OPS_BASIS = AMD64DarwinPseudoOps (
146      structure T = T      structure T = T
147      structure MLTreeEval = MLTreeEval)      structure MLTreeEval = MLTreeEval)
148    *)
149    
150  structure AMD64PseudoOps = AMD64PseudoOpsFn(  structure AMD64PseudoOps = AMD64PseudoOpsFn(
151              structure T = AMD64MLTree              structure T = AMD64MLTree
# Line 197  Line 197 
197              structure InsnProps = AMD64InsnProps              structure InsnProps = AMD64InsnProps
198              structure Asm = AMD64Asm)              structure Asm = AMD64Asm)
199    
 (*structure AMD64Stream = InstructionStream(AMD64PseudoOps)*)  
200  structure AMD64MLTStream = MLTreeStream (  structure AMD64MLTStream = MLTreeStream (
201                        structure T = AMD64MLTree                        structure T = AMD64MLTree
202                        structure S = AMD64Stream)                        structure S = AMD64Stream)
# Line 329  Line 328 
328  structure CCalls = AMD64SVIDFn (  structure CCalls = AMD64SVIDFn (
329                      structure T = AMD64MLTree)                      structure T = AMD64MLTree)
330    
331  (*  
332  structure CCalls = AMD64SVID (  structure OldCCalls = AMD64SVID (
333             structure T = AMD64MLTree             structure T = AMD64MLTree
334             val frameAlign = 16)             val frameAlign = 16)
335  *)  
336    
337  structure RA2 =  structure RA2 =
338      RISC_RA      RISC_RA
# Line 494  Line 493 
493  structure CFG = AMD64CFG  structure CFG = AMD64CFG
494  structure FlowGraph = AMD64FlowGraph  structure FlowGraph = AMD64FlowGraph
495  structure ChkTy = MLTreeCheckTy(structure T = T val intTy = 64)  structure ChkTy = MLTreeCheckTy(structure T = T val intTy = 64)
496  structure Vararg = AMD64VarargCCallFn(structure T = T)  structure Vararg = AMD64VarargCCallFn(
497                           structure T = T
498                           fun push e = T.EXT(AMD64InstrExt.PUSHQ e)
499                           val leave = T.EXT(AMD64InstrExt.LEAVE)
500                       )
501    
502  structure TestStagedAllocation =  structure TestSA =
503    struct    struct
504    
505      val wordTy = 64      val wordTy = 64
# Line 570  Line 573 
573    
574      fun lit i = T.LI (T.I.fromInt (wordTy, i))      fun lit i = T.LI (T.I.fromInt (wordTy, i))
575    
576     fun testVarargs _ = let     fun vararg _ = let
577             val lab = Label.global "varargs"             val _ = Label.reset()
578             val tmp = C.newReg()             val (lab, varargStms) = Vararg.genVarargs()
            val tmpC = C.newReg()  
            val preCallInstrs = [T.MV(wordTy, C.rax, lit (List.length CCalls.CCs.fprParams))]  
            val stms =  
                List.concat [  
                    [T.EXT(AMD64InstrExt.PUSHQ(T.REG(64, Cells.rbp))),  
                     T.COPY (wordTy, [Cells.rbp], [Cells.rsp])],  
                    [T.MV(wordTy, tmp, T.REG(wordTy, C.rsi))],  
                    [T.MV(wordTy, tmpC, T.REG(wordTy, C.rdi))],  
                    Vararg.genVarArgs (T.REG(wordTy, tmpC), tmp, preCallInstrs),  
                    [T.EXT(AMD64InstrExt.LEAVE)],  
                    [T.RET []]  
                    ]  
   
579             val asmOutStrm = TextIO.openOut "mlrisc.s"             val asmOutStrm = TextIO.openOut "mlrisc.s"
580             fun doit () = dumpOutput(gen(lab, stms, [T.GPR (T.REG (wordTy, C.rax))]))             fun doit () = dumpOutput(gen(lab, varargStms, [T.GPR (T.REG (wordTy, C.rax))]))
581             val _ = AsmStream.withStream asmOutStrm doit ()             val _ = AsmStream.withStream asmOutStrm doit ()
582             val _ = TextIO.closeOut asmOutStrm             val _ = TextIO.closeOut asmOutStrm
583             in             in
584                0                0
585             end             end
   
586    end    end
587    
588    
# Line 605  Line 594 
594      (* maximum argument size in machine words *)      (* maximum argument size in machine words *)
595      val maxArgSz = 16      val maxArgSz = 16
596      val maxArgSzB = maxArgSz * wordSzB      val maxArgSzB = maxArgSz * wordSzB
597    (*
598  (* unit testing code *)  (* unit testing code *)
599  structure Test =  structure Test =
600    struct    struct
# Line 660  Line 649 
649                 ListPair.all test (List.map slotsOfCTy ts, anss) orelse raise Fail "failed test"                 ListPair.all test (List.map slotsOfCTy ts, anss) orelse raise Fail "failed test"
650              end              end
651    end    end
652    *)
653    
654    structure Test = struct end

Legend:
Removed from v.3042  
changed lines
  Added in v.3058

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0