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[smlnj] Annotation of /MLRISC/trunk/c-call/varargs/call/vararg-call.sml
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Annotation of /MLRISC/trunk/c-call/varargs/call/vararg-call.sml

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Revision 3137 - (view) (download)

1 : mrainey 3137 structure VarargCall =
2 :     struct
3 :    
4 :     val regNum = CellsBasis.physicalRegisterNum
5 :    
6 :     structure X86SA = StagedAllocationFn (
7 :     type reg_id = int
8 :     datatype loc_kind = datatype CLocKind.loc_kind
9 :     val memSize = 8)
10 :     structure X86Convention = X86CConventionFn(
11 :     type reg_id = int
12 :     val eax = regNum X86Cells.eax
13 :     val edx = regNum X86Cells.edx
14 :     val st0 = regNum X86Cells.ST0
15 :     structure SA = X86SA)
16 :     structure X86VarargCall = VarargCallFn (
17 :     val params = X86Convention.params
18 :     val returns = X86Convention.returns
19 :     val store0 = X86Convention.store0
20 :     val bitWidthOfPointer = 32
21 :     val alignBOfPointer = 4
22 :     val alignBOfInt = 4
23 :     val alignBOfDouble = 4
24 :     val kindOfInt = CLocKind.GPR
25 :     val kindOfPointer = CLocKind.GPR
26 :     val kindOfDouble = CLocKind.FPR
27 :     structure SA = X86SA
28 :     )
29 :    
30 :     structure X86_64SA = StagedAllocationFn (
31 :     type reg_id = int
32 :     datatype loc_kind = datatype CLocKind.loc_kind
33 :     val memSize = 8)
34 :     structure X86_64Convention = X86_64CConventionFn(
35 :     type reg_id = int
36 :     val rax = regNum AMD64Cells.rax
37 :     val rdi = regNum AMD64Cells.rdi
38 :     val rsi = regNum AMD64Cells.rsi
39 :     val rdx = regNum AMD64Cells.rdx
40 :     val rcx = regNum AMD64Cells.rcx
41 :     val r8 = regNum AMD64Cells.r8
42 :     val r9 = regNum AMD64Cells.r9
43 :     val xmm0 = regNum AMD64Cells.xmm0
44 :     val xmm1 = regNum AMD64Cells.xmm1
45 :     val xmm2 = regNum AMD64Cells.xmm2
46 :     val xmm3 = regNum AMD64Cells.xmm3
47 :     val xmm4 = regNum AMD64Cells.xmm4
48 :     val xmm5 = regNum AMD64Cells.xmm5
49 :     val xmm6 = regNum AMD64Cells.xmm6
50 :     val xmm7 = regNum AMD64Cells.xmm7
51 :     structure SA = X86_64SA)
52 :     structure X86_64VarargCall = VarargCallFn (
53 :     val params = X86_64Convention.params
54 :     val returns = X86_64Convention.returns
55 :     val store0 = X86_64Convention.store0
56 :     val bitWidthOfPointer = 64
57 :     val alignBOfPointer = 8
58 :     val alignBOfInt = 8
59 :     val alignBOfDouble = 8
60 :     val kindOfInt = CLocKind.GPR
61 :     val kindOfPointer = CLocKind.GPR
62 :     val kindOfDouble = CLocKind.FPR
63 :     structure SA = X86_64SA
64 :     )
65 :    
66 :     local
67 :     structure V = Vararg
68 :     structure DL = DynLinkage
69 :     fun main's s = DL.lib_symbol (DL.main_lib, s)
70 :     val printf_h = main's "printf"
71 :     fun call args = X86VarargCall.dispatchLowlevelCall(printf_h, args)
72 :     in
73 :     fun ex1 () = call [V.STRING_ARG "test123\n"]
74 :     fun ex2 () = call [V.STRING_ARG "%d %s\n", V.SINT_ARG 1024, V.STRING_ARG "xxx"]
75 :     fun ex3 () = call [V.STRING_ARG "%d %s %d\n", V.SINT_ARG 1024, V.STRING_ARG "xxx", V.SINT_ARG 222333]
76 :     end
77 :    
78 :     end

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