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[smlnj] Diff of /MLRISC/trunk/staged-allocation/test-staged-allocation-amd64.sml
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Diff of /MLRISC/trunk/staged-allocation/test-staged-allocation-amd64.sml

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revision 2999, Sun Apr 20 19:35:47 2008 UTC revision 3000, Tue Apr 22 08:01:00 2008 UTC
# Line 38  Line 38 
38  end (* AMD64PseudoOps *)  end (* AMD64PseudoOps *)
39  *)  *)
40    
41  (*  
42  functor AMD64PseudoOpsFn (  functor AMD64PseudoOpsFn (
43      structure T : MLTREE      structure T : MLTREE
44      structure MLTreeEval : MLTREE_EVAL where T = T      structure MLTreeEval : MLTREE_EVAL where T = T
45    ) : PSEUDO_OPS_BASIS = AMD64GasPseudoOps (    ) : PSEUDO_OPS_BASIS = AMD64GasPseudoOps (
46      structure T = T      structure T = T
47      structure MLTreeEval = MLTreeEval)      structure MLTreeEval = MLTreeEval)
 *)  
48    
49    (*
50  functor AMD64PseudoOpsFn (  functor AMD64PseudoOpsFn (
51      structure T : MLTREE      structure T : MLTREE
52      structure MLTreeEval : MLTREE_EVAL where T = T      structure MLTreeEval : MLTREE_EVAL where T = T
53    ) : PSEUDO_OPS_BASIS = AMD64DarwinPseudoOps (    ) : PSEUDO_OPS_BASIS = AMD64DarwinPseudoOps (
54      structure T = T      structure T = T
55      structure MLTreeEval = MLTreeEval)      structure MLTreeEval = MLTreeEval)
56    *)
57    
58  structure AMD64PseudoOps = AMD64PseudoOpsFn(  structure AMD64PseudoOps = AMD64PseudoOpsFn(
59              structure T = AMD64MLTree              structure T = AMD64MLTree
# Line 237  Line 237 
237  structure CCalls = AMD64SVID (  structure CCalls = AMD64SVID (
238             structure T = AMD64MLTree             structure T = AMD64MLTree
239             val frameAlign = 16)             val frameAlign = 16)
240    
241    
242    structure RA2 =
243        RISC_RA
244        (structure I = AMD64Instr
245         structure Asm = AMD64Asm
246         structure CFG = AMD64CFG
247         structure InsnProps = AMD64InsnProps
248         structure Rewrite =
249           struct
250             structure I = AMD64Instr
251             fun rewriteDef _ = raise Fail ""
252             fun rewriteUse _ = raise Fail ""
253             fun frewriteDef _ = raise Fail ""
254             fun frewriteUse _ = raise Fail ""
255           end
256         structure SpillInstr = AMD64SpillInstr (
257                   structure I = I
258                   structure Props = AMD64InsnProps
259                   val floats16ByteAligned = true)
260         structure SpillHeur = ChaitinSpillHeur
261         structure Spill = RASpill (structure InsnProps = AMD64InsnProps
262                                    structure Asm = AMD64Asm)
263    
264         datatype spillOperandKind = SPILL_LOC | CONST_VAL
265         type spill_info = unit
266         fun beforeRA _ = raise Fail ""
267    
268         val architecture = "amd64"
269         fun pure _ = true
270    
271         structure Int =
272            struct
273              val avail = []
274              val dedicated = []
275              fun spillLoc _ = raise Fail ""
276              val mode = RACore.NO_OPTIMIZATION
277            end
278         structure Float =
279            struct
280              val avail = []
281              val dedicated = []
282              fun spillLoc _ = raise Fail ""
283              val mode = RACore.NO_OPTIMIZATION
284            end
285    
286        )
287    

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