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[smlnj] Diff of /MLRISC/trunk/staged-allocation/test-staged-allocation.sml
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Diff of /MLRISC/trunk/staged-allocation/test-staged-allocation.sml

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revision 3007, Mon Apr 28 15:29:41 2008 UTC revision 3008, Mon Apr 28 19:40:46 2008 UTC
# Line 10  Line 10 
10      fun codegen (functionName, target, proto, initStms, args) = let      fun codegen (functionName, target, proto, initStms, args) = let
11          val _ = Label.reset()          val _ = Label.reset()
12    
13          fun toLabel s = Label.global(s)          val [functionName, target] = List.map Label.global [functionName, target]
         val [functionName, target] = List.map toLabel [functionName, target]  
14    
15          val insnStrm = AMD64FlowGraph.build()          val insnStrm = AMD64FlowGraph.build()
16          (* construct the C call *)          (* construct the C call *)
# Line 26  Line 25 
25    
26          fun wordLit i = T.LI (T.I.fromInt (wordTy, i))          fun wordLit i = T.LI (T.I.fromInt (wordTy, i))
27    
         fun mv () = let  
             val r = C.newReg()  
             in  
                 [T.MV(wordTy, r, T.LOAD(wordTy, T.REG(wordTy, C.rsp), ())),  
                  T.MV(wordTy, C.rax, T.REG(wordTy, r))  
                 ]  
             end  
   
         val fr = C.FPReg 10  
   
         fun fmv () = let  
             val r = C.newFreg()  
             in  
                 [T.FMV(32, r, T.FLOAD(32, T.REG(wordTy, C.rsp), ())),  
                  T.FMV(32, fr, T.FREG(32, r))  
                 ]  
             end  
   
28          val stms = List.concat [          val stms = List.concat [
29                     [T.EXT(AMD64InstrExt.PUSHQ(T.REG(64, C.rbp))),                     [T.EXT(AMD64InstrExt.PUSHQ(T.REG(64, C.rbp))),
30                      T.COPY (wordTy, [C.rbp], [C.rsp])],                      T.COPY (wordTy, [C.rbp], [C.rsp])],
31                     initStms,                     initStms,
32                     callseq,                     callseq,
 (*                  mv(), *)  
33                     [T.EXT(AMD64InstrExt.LEAVE)],                     [T.EXT(AMD64InstrExt.LEAVE)],
34                     [T.RET []]]                     [T.RET []]]
35    
# Line 70  Line 50 
50              pseudoOp (PseudoOpsBasisTyp.EXPORT [functionName]);              pseudoOp (PseudoOpsBasisTyp.EXPORT [functionName]);
51              entryLabel functionName; (* define the entry label *)              entryLabel functionName; (* define the entry label *)
52              List.app emit stms; (* emit all the statements *)              List.app emit stms; (* emit all the statements *)
53              exitBlock (T.FPR (T.FREG (32, fr)) :: T.GPR (T.REG (32, C.rax)) :: result);              exitBlock result;
54              endCluster [])              endCluster [])
55          val cfg = doit ()          val cfg = doit ()
56          val cfg = AMD64RA.run cfg          val cfg = AMD64RA.run cfg

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