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[diderot] Annotation of /branches/vis15/src/compiler/target-cpu/target-cpu.sml
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Annotation of /branches/vis15/src/compiler/target-cpu/target-cpu.sml

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1 : jhr 3901 (* target-cpu.sml
2 : jhr 3864 *
3 :     * Code generation for the sequential and parallel targets.
4 :     *
5 :     * This code is part of the Diderot Project (http://diderot-language.cs.uchicago.edu)
6 :     *
7 :     * COPYRIGHT (c) 2016 The University of Chicago
8 :     * All rights reserved.
9 :     *)
10 :    
11 : jhr 3901 structure TargetCPU : sig
12 : jhr 3864
13 :     val target : TargetOptions.t -> {
14 :     info : TreeIR.target_info,
15 :     generate : TreeIR.program -> unit
16 :     }
17 :    
18 :     end = struct
19 :    
20 :     structure Spec = TargetSpec
21 :    
22 : jhr 3902 fun generate (tgt : TargetOptions.t) (prog as TreeIR.Program{props, ...}) = let
23 : jhr 3864 val spec = TargetSpec.mk (tgt, props)
24 :     in
25 : jhr 3901 if (#exec spec)
26 : jhr 3902 then Gen.exec (spec, prog)
27 :     else Gen.library (spec, prog)
28 : jhr 3864 end
29 :    
30 :     fun info (tgt : TargetOptions.t) = {
31 :     layout = if (#scalar tgt)
32 : jhr 3901 then VectorLayout.scalar
33 :     else VectorLayout.layout (VectorLayout.gccVectorSizes (#double tgt)),
34 : jhr 3864 isInline =
35 : jhr 4025 fn LowOps.RealToInt d => (d = 1) (* because it produces an array when d > 1 *)
36 : jhr 3950 | LowOps.EigenVecs2x2 => false
37 : jhr 3864 | LowOps.EigenVecs3x3 => false
38 :     | LowOps.EigenVals2x2 => false
39 :     | LowOps.EigenVals3x3 => false
40 : jhr 3901 | LowOps.Zero _ => false
41 : jhr 3864 | _ => true
42 :     }
43 :    
44 :     fun target tgt = {
45 :     info = info tgt,
46 :     generate = generate tgt
47 :     }
48 :    
49 :     end

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