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View of /branches/vis15/src/compiler/target-cpu/target-cpu.sml

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Revision 3950 - (download) (annotate)
Sat Jun 11 16:02:12 2016 UTC (3 years, 2 months ago) by jhr
File size: 1200 byte(s)
working on merge: code generation
(* target-cpu.sml
 *
 * Code generation for the sequential and parallel targets.
 *
 * This code is part of the Diderot Project (http://diderot-language.cs.uchicago.edu)
 *
 * COPYRIGHT (c) 2016 The University of Chicago
 * All rights reserved.
 *)

structure TargetCPU : sig

    val target : TargetOptions.t -> {
	    info : TreeIR.target_info,
	    generate : TreeIR.program -> unit
	  }

  end = struct

    structure Spec = TargetSpec

    fun generate (tgt : TargetOptions.t) (prog as TreeIR.Program{props, ...}) = let
	  val spec = TargetSpec.mk (tgt, props)
	  in
	    if (#exec spec)
	      then Gen.exec (spec, prog)
	      else Gen.library (spec, prog)
	  end

    fun info (tgt : TargetOptions.t) = {
	    layout = if (#scalar tgt)
		then VectorLayout.scalar
		else VectorLayout.layout (VectorLayout.gccVectorSizes (#double tgt)),
	    isInline =
	       fn LowOps.RealToInt d => (d > 1) (* because it produces an array *)
		| LowOps.EigenVecs2x2 => false
		| LowOps.EigenVecs3x3 => false
		| LowOps.EigenVals2x2 => false
		| LowOps.EigenVals3x3 => false
		| LowOps.Zero _ => false
		| _ => true
	  }

    fun target tgt = {
	    info = info tgt,
	    generate = generate tgt
	  }

  end

root@smlnj-gforge.cs.uchicago.edu
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