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Thu Oct 11 09:52:12 2001 UTC (18 years, 11 months ago) by macqueen
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<!DOCTYPE HTML  PUBLIC "-//IETF//DTD HTML//EN">
   <html>
     <head>         <title>Pentium II Performance Counters</title>
     </head>
   <body bgcolor="white">
      <center><h1>Pentium II Performance Counters<BR>
                   May 28, 1999</h1>
      </center>
   <blockquote>
    <p>
     <table border><tr> <th>  <th> barnes-hut <th> boyer <th> count-graphs <th> fft <th> logic <th> mandelbrot <th> ratio-regions <th> ray <th> simple <th> tsp</tr>
<tr><td> data_mem_refs<td align=right> 664048<td align=right> 56049<td align=right> 9756930<td align=right> 222204<td align=right> 1352590<td align=right> 282606<td align=right> 26538600<td align=right> 682891<td align=right> 35998<td align=right> 1376880</tr>

<tr><td> dcu_lines_in<td align=right> 24184<td align=right> 1875<td align=right> 194801<td align=right> 5130<td align=right> 38072<td align=right> 3206<td align=right> 724545<td align=right> 21739<td align=right> 728<td align=right> 37484</tr>

<tr><td> dcu_m_lines_in<td align=right> 16925<td align=right> 1153<td align=right> 188501<td align=right> 2707<td align=right> 28979<td align=right> 3128<td align=right> 609538<td align=right> 19558<td align=right> 618<td align=right> 29716</tr>

<tr><td> dcu_m_lines_out<td align=right> 17209<td align=right> 1283<td align=right> 188831<td align=right> 4868<td align=right> 29812<td align=right> 3140<td align=right> 629231<td align=right> 19691<td align=right> 640<td align=right> 30039</tr>

<tr><td> dcu_miss_outstanding<td align=right> 245026<td align=right> 24082<td align=right> 253944<td align=right> 134753<td align=right> 310115<td align=right> 3251<td align=right> 6428190<td align=right> 71520<td align=right> 8715<td align=right> 264805</tr>

<tr><td> ifu_ifetch<td align=right> 737629<td align=right> 58128<td align=right> 8049090<td align=right> 201142<td align=right> 1153200<td align=right> 176616<td align=right> 27629600<td align=right> 787456<td align=right> 33559<td align=right> 1549800</tr>

<tr><td> ifu_ifetch_miss<td align=right> 87<td align=right> 34<td align=right> 3181<td align=right> 39<td align=right> 2104<td align=right> 32<td align=right> 8150<td align=right> 77<td align=right> 36<td align=right> 47</tr>

<tr><td> itlb_miss<td align=right> 19<td align=right> 8<td align=right> 51<td align=right> 9<td align=right> 27<td align=right> 6<td align=right> 35<td align=right> 14<td align=right> 10<td align=right> 12</tr>

<tr><td> ifu_mem_stall<td align=right> 10304<td align=right> 1959<td align=right> 264974<td align=right> 2802<td align=right> 476519<td align=right> 1657<td align=right> 324989<td align=right> 10129<td align=right> 2199<td align=right> 4377</tr>

<tr><td> ild_stall<td align=right> 314<td align=right> 187<td align=right> 359<td align=right> 74<td align=right> 1843<td align=right> 70<td align=right> 48289<td align=right> 1125<td align=right> 74<td align=right> 765</tr>

<tr><td> l2_ifetch<td align=right> 252<td align=right> 99<td align=right> 8945<td align=right> 120<td align=right> 19540<td align=right> 94<td align=right> 22972<td align=right> 233<td align=right> 104<td align=right> 133</tr>

<tr><td> l2_ld<td align=right> 9547<td align=right> 817<td align=right> 14062<td align=right> 3022<td align=right> 10096<td align=right> 82<td align=right> 189121<td align=right> 5315<td align=right> 167<td align=right> 14732</tr>

<tr><td> l2_st<td align=right> 14659<td align=right> 1058<td align=right> 180730<td align=right> 2108<td align=right> 27965<td align=right> 3124<td align=right> 535441<td align=right> 16406<td align=right> 561<td align=right> 22774</tr>

<tr><td> l2_lines_in<td align=right> 16765<td align=right> 1115<td align=right> 174674<td align=right> 3554<td align=right> 28352<td align=right> 3074<td align=right> 621987<td align=right> 18803<td align=right> 631<td align=right> 29282</tr>

<tr><td> l2_lines_out<td align=right> 16734<td align=right> 1113<td align=right> 179885<td align=right> 3564<td align=right> 29024<td align=right> 3092<td align=right> 616644<td align=right> 18411<td align=right> 640<td align=right> 28243</tr>

<tr><td> l2_m_lines_inm<td align=right> 15874<td align=right> 1037<td align=right> 174582<td align=right> 3418<td align=right> 27035<td align=right> 3042<td align=right> 585729<td align=right> 18121<td align=right> 584<td align=right> 27999</tr>

<tr><td> l2_m_lines_outm<td align=right> 16040<td align=right> 1058<td align=right> 175064<td align=right> 3440<td align=right> 27565<td align=right> 3078<td align=right> 584228<td align=right> 18077<td align=right> 604<td align=right> 27411</tr>

<tr><td> l2_rqsts<td align=right> 24433<td align=right> 1972<td align=right> 203765<td align=right> 5249<td align=right> 57602<td align=right> 3299<td align=right> 747543<td align=right> 21972<td align=right> 832<td align=right> 37621</tr>

<tr><td> l2_ads<td align=right> 108141<td align=right> 7927<td align=right> 1132820<td align=right> 26026<td align=right> 202411<td align=right> 18751<td align=right> 3892030<td align=right> 117700<td align=right> 4022<td align=right> 185464</tr>

<tr><td> l2_dbus_busy<td align=right> 492255<td align=right> 37057<td align=right> 4787760<td align=right> 125505<td align=right> 948679<td align=right> 76203<td align=right> 17721200<td align=right> 515973<td align=right> 17697<td align=right> 839487</tr>

<tr><td> l2_dmus_busy_rd<td align=right> 333632<td align=right> 25555<td align=right> 3192850<td align=right> 74521<td align=right> 684155<td align=right> 50913<td align=right> 11671100<td align=right> 335868<td align=right> 11709<td align=right> 539834</tr>

<tr><td> bus_drdy_clocks<td align=right> 63960<td align=right> 4262<td align=right> 709845<td align=right> 13651<td align=right> 106099<td align=right> 12215<td align=right> 2330830<td align=right> 71421<td align=right> 2389<td align=right> 111170</tr>

<tr><td> bus_lock_clocks<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0</tr>

<tr><td> bus_req_outstanding<td align=right> 209335<td align=right> 10738<td align=right> 675022<td align=right> 117396<td align=right> 199603<td align=right> 1775<td align=right> 10564200<td align=right> 231323<td align=right> 6477<td align=right> 585893</tr>

<tr><td> bus_tran_brd<td align=right> 2804<td align=right> 166<td align=right> 10206<td align=right> 1555<td align=right> 3316<td align=right> 41<td align=right> 127995<td align=right> 3023<td align=right> 107<td align=right> 7833</tr>

<tr><td> bus_tran_rfo<td align=right> 13683<td align=right> 957<td align=right> 166461<td align=right> 1945<td align=right> 25279<td align=right> 3005<td align=right> 493652<td align=right> 15229<td align=right> 520<td align=right> 21195</tr>

<tr><td> bus_trans_wb<td align=right> 15960<td align=right> 1067<td align=right> 175679<td align=right> 3437<td align=right> 27120<td align=right> 3024<td align=right> 584872<td align=right> 18056<td align=right> 598<td align=right> 28214</tr>

<tr><td> bus_tran_ifetch<td align=right> 123<td align=right> 21<td align=right> 1956<td align=right> 29<td align=right> 457<td align=right> 17<td align=right> 937<td align=right> 119<td align=right> 21<td align=right> 44</tr>

<tr><td> bus_tran_inval<td align=right> 0<td align=right> 0<td align=right> 2<td align=right> 0<td align=right> 15<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0</tr>

<tr><td> bus_tran_pwr<td align=right> 0<td align=right> 0<td align=right> 1<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 2<td align=right> 0<td align=right> 0<td align=right> 0</tr>

<tr><td> bus_trans_p<td align=right> 0<td align=right> 0<td align=right> 2<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 7<td align=right> 0<td align=right> 32<td align=right> 0</tr>

<tr><td> bus_trans_io<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0</tr>

<tr><td> bus_trans_def<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0</tr>

<tr><td> bus_tran_burst<td align=right> 33013<td align=right> 2185<td align=right> 352387<td align=right> 6927<td align=right> 54723<td align=right> 6116<td align=right> 1213790<td align=right> 36559<td align=right> 1251<td align=right> 56698</tr>

<tr><td> bus_tran_any<td align=right> 32642<td align=right> 2173<td align=right> 347949<td align=right> 7046<td align=right> 56144<td align=right> 6153<td align=right> 1212270<td align=right> 36178<td align=right> 1286<td align=right> 55947</tr>

<tr><td> bus_tran_mem<td align=right> 32684<td align=right> 2180<td align=right> 355448<td align=right> 7004<td align=right> 55802<td align=right> 6194<td align=right> 1214030<td align=right> 36459<td align=right> 1251<td align=right> 56134</tr>

<tr><td> bus_data_rcv<td align=right> 66333<td align=right> 4448<td align=right> 715605<td align=right> 14157<td align=right> 112800<td align=right> 12293<td align=right> 2487190<td align=right> 73684<td align=right> 2606<td align=right> 114887</tr>

<tr><td> bus_bnr_drv<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0</tr>

<tr><td> bus_hit_drv<td align=right> 1<td align=right> 1<td align=right> 3<td align=right> 0<td align=right> 1<td align=right> 0<td align=right> 8<td align=right> 1<td align=right> 31<td align=right> 1</tr>

<tr><td> bus_hitm_drv<td align=right> 1<td align=right> 0<td align=right> 3<td align=right> 0<td align=right> 1<td align=right> 0<td align=right> 9<td align=right> 1<td align=right> 31<td align=right> 1</tr>

<tr><td> bus_snoop_stall<td align=right> 1<td align=right> 0<td align=right> 3<td align=right> 0<td align=right> 1<td align=right> 0<td align=right> 11<td align=right> 1<td align=right> 31<td align=right> 1</tr>

<tr><td> comp_flop_ret<td align=right> 31134<td align=right> 0<td align=right> 0<td align=right> 19433<td align=right> 0<td align=right> 39123<td align=right> 1<td align=right> 46137<td align=right> 847<td align=right> 89836</tr>

<tr><td> flops<td align=right> 32031<td align=right> 18<td align=right> 36<td align=right> 19988<td align=right> 18<td align=right> 39147<td align=right> 8793<td align=right> 46858<td align=right> 1009<td align=right> 93592</tr>

<tr><td> fp_assist<td align=right> 1<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 1<td align=right> 0<td align=right> 0</tr>

<tr><td> mul<td align=right> 8403<td align=right> 1<td align=right> 18<td align=right> 6963<td align=right> 1<td align=right> 15840<td align=right> 8771<td align=right> 15468<td align=right> 451<td align=right> 20391</tr>

<tr><td> div<td align=right> 68980<td align=right> 297<td align=right> 302<td align=right> 6827<td align=right> 298<td align=right> 297<td align=right> 363<td align=right> 61499<td align=right> 492<td align=right> 206676</tr>

<tr><td> cycles_div_busy<td align=right> 131731<td align=right> 578<td align=right> 587<td align=right> 13113<td align=right> 579<td align=right> 577<td align=right> 706<td align=right> 118262<td align=right> 947<td align=right> 398229</tr>

<tr><td> ld_blocks<td align=right> 179781<td align=right> 10519<td align=right> 1780370<td align=right> 70630<td align=right> 375772<td align=right> 90826<td align=right> 5870970<td align=right> 187238<td align=right> 9852<td align=right> 426194</tr>

<tr><td> sb_drains<td align=right> 14<td align=right> 7<td align=right> 90<td align=right> 8<td align=right> 20<td align=right> 7<td align=right> 337<td align=right> 14<td align=right> 16<td align=right> 18</tr>

<tr><td> misalign_mem_ref<td align=right> 1<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 1<td align=right> 1<td align=right> 0<td align=right> 3</tr>

<tr><td> inst_retired<td align=right> 501617<td align=right> 44721<td align=right> 7137310<td align=right> 160226<td align=right> 1069880<td align=right> 225369<td align=right> 22420900<td align=right> 524488<td align=right> 29702<td align=right> 1122230</tr>

<tr><td> uops_retired<td align=right> 1268330<td align=right> 112128<td align=right> 17465300<td align=right> 402579<td align=right> 2538300<td align=right> 559027<td align=right> 53022800<td align=right> 1339200<td align=right> 71479<td align=right> 2845360</tr>

<tr><td> inst_decoder<td align=right> 1097990<td align=right> 93542<td align=right> 14537700<td align=right> 315063<td align=right> 2639440<td align=right> 403797<td align=right> 49356800<td align=right> 1136580<td align=right> 57439<td align=right> 2429960</tr>

<tr><td> hw_int_rx<td align=right> 0<td align=right> 0<td align=right> 4<td align=right> 0<td align=right> 1<td align=right> 0<td align=right> 14<td align=right> 0<td align=right> 0<td align=right> 1</tr>

<tr><td> cycles_int_masked<td align=right> 24<td align=right> 2<td align=right> 383<td align=right> 11<td align=right> 66<td align=right> 9<td align=right> 1534<td align=right> 43<td align=right> 1<td align=right> 88</tr>

<tr><td> cycles_int_pending_and_masked<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0<td align=right> 0</tr>

<tr><td> br_inst_retired<td align=right> 100686<td align=right> 9578<td align=right> 1349940<td align=right> 31641<td align=right> 227252<td align=right> 49031<td align=right> 5017710<td align=right> 92078<td align=right> 7140<td align=right> 244363</tr>

<tr><td> br_miss_pred_retired<td align=right> 9092<td align=right> 916<td align=right> 102014<td align=right> 1019<td align=right> 34428<td align=right> 117<td align=right> 446055<td align=right> 10382<td align=right> 366<td align=right> 13545</tr>

<tr><td> br_taken_retired<td align=right> 52413<td align=right> 5874<td align=right> 872836<td align=right> 19783<td align=right> 126170<td align=right> 25321<td align=right> 2990660<td align=right> 50792<td align=right> 4641<td align=right> 119092</tr>

<tr><td> br_miss_pred_taken_ret<td align=right> 7084<td align=right> 658<td align=right> 81697<td align=right> 914<td align=right> 28843<td align=right> 73<td align=right> 439830<td align=right> 9800<td align=right> 323<td align=right> 10790</tr>

<tr><td> br_inst_decoded<td align=right> 112375<td align=right> 11296<td align=right> 1545180<td align=right> 32944<td align=right> 311561<td align=right> 49404<td align=right> 5816830<td align=right> 105553<td align=right> 7879<td align=right> 259505</tr>

<tr><td> btb_misses<td align=right> 45056<td align=right> 2120<td align=right> 340698<td align=right> 9786<td align=right> 116077<td align=right> 14220<td align=right> 1975100<td align=right> 44715<td align=right> 2444<td align=right> 109829</tr>

<tr><td> br_bogus<td align=right> 63<td align=right> 0<td align=right> 1<td align=right> 0<td align=right> 1711<td align=right> 0<td align=right> 3352<td align=right> 0<td align=right> 0<td align=right> 0</tr>

<tr><td> baclears<td align=right> 172<td align=right> 68<td align=right> 1714<td align=right> 80<td align=right> 10300<td align=right> 66<td align=right> 12758<td align=right> 91<td align=right> 71<td align=right> 82</tr>

<tr><td> resource_stalls<td align=right> 757942<td align=right> 51464<td align=right> 7065700<td align=right> 222883<td align=right> 711854<td align=right> 93831<td align=right> 25100400<td align=right> 789276<td align=right> 28834<td align=right> 1381840</tr>

<tr><td> partial_rat_stalls<td align=right> 7539<td align=right> 6328<td align=right> 25833<td align=right> 1961<td align=right> 100519<td align=right> 1886<td align=right> 1729830<td align=right> 2013<td align=right> 1955<td align=right> 28718</tr>

<tr><td> segment_reg_loads<td align=right> 15<td align=right> 12<td align=right> 39<td align=right> 13<td align=right> 21<td align=right> 11<td align=right> 114<td align=right> 13<td align=right> 11<td align=right> 19</tr>

<tr><td> cpu_clk_unhalted<td align=right> 1504190<td align=right> 118767<td align=right> 16419800<td align=right> 403561<td align=right> 2779990<td align=right> 355328<td align=right> 55343900<td align=right> 1600600<td align=right> 69937<td align=right> 3163400</tr>

</table>
    <hr>
    <font size=-2>
    <address><a href="mailto:george@research.bell-labs.com">Lal George</a></address>
    </font>
   </blockquote>
  </body></html>

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