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[smlnj] Diff of /sml/branches/SMLNJ/src/MLRISC/alpha32/alpha32.sml
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Diff of /sml/branches/SMLNJ/src/MLRISC/alpha32/alpha32.sml

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revision 105, Thu May 28 21:30:17 1998 UTC revision 106, Thu May 28 21:30:17 1998 UTC
# Line 26  Line 26 
26    structure C = Alpha32Instr.C    structure C = Alpha32Instr.C
27    structure LE = LabelExp    structure LE = LabelExp
28    structure W32 = Word32    structure W32 = Word32
29    
30   (*********************************************************   (*********************************************************
31    
32         Trap Shadows, Floating Exceptions, and Denormalized         Trap Shadows, Floating Exceptions, and Denormalized
# Line 130  Line 131 
131    
132    val emit = F.emitInstr    val emit = F.emitInstr
133    
   fun newReg () = C.newReg()  
   fun newFreg() = C.newFreg()  
   
134    val zeroR = 31    val zeroR = 31
135    val zeroOp = I.REGop zeroR    val zeroOp = I.REGop zeroR
136    val zeroEA = I.Direct zeroR    val zeroEA = I.Direct zeroR
# Line 205  Line 203 
203      fun fbranch(_, T.FCMP(cc, exp1, exp2, order), lab) = let      fun fbranch(_, T.FCMP(cc, exp1, exp2, order), lab) = let
204        val (f1, f2) = orderedFArith(exp1, exp2, order)        val (f1, f2) = orderedFArith(exp1, exp2, order)
205        fun bcc(cmp, br) = let        fun bcc(cmp, br) = let
206          val tmpR = newFreg()          val tmpR = C.newFreg()
207        in        in
208          emit(I.DEFFREG(tmpR));          emit(I.DEFFREG(tmpR));
209          emit(I.FOPERATE{oper=cmp, fa=f1, fb=f2, fc=tmpR});          emit(I.FOPERATE{oper=cmp, fa=f1, fb=f2, fc=tmpR});
# Line 214  Line 212 
212        end        end
213    
214        fun fall(cmp1, br1, cmp2, br2) = let        fun fall(cmp1, br1, cmp2, br2) = let
215          val tmpR1 = newFreg()          val tmpR1 = C.newFreg()
216          val tmpR2 = newFreg()          val tmpR2 = C.newFreg()
217          val fallLab = Label.newLabel ""          val fallLab = Label.newLabel ""
218        in        in
219          emit(I.DEFFREG(tmpR1));          emit(I.DEFFREG(tmpR1));
# Line 250  Line 248 
248    
249      fun branch(cond, exp1, exp2, lab, order) = let      fun branch(cond, exp1, exp2, lab, order) = let
250          fun zapHi r = emit(I.OPERATE{oper=I.ZAP, ra=r, rb=I.IMMop 0xf0, rc=r})          fun zapHi r = emit(I.OPERATE{oper=I.ZAP, ra=r, rb=I.IMMop 0xf0, rc=r})
251          val tmpR = newReg()          val tmpR = C.newReg()
252          val (r1, o2) =          val (r1, o2) =
253            case order            case order
254             of T.LR => (regAction exp1, opndAction exp2)             of T.LR => (regAction exp1, opndAction exp2)
# Line 279  Line 277 
277            | I.CC_EQ  => emitBr(I.CMPEQ,  I.BNE)            | I.CC_EQ  => emitBr(I.CMPEQ,  I.BNE)
278            | I.CC_NEQ => emitBr(I.CMPEQ,  I.BEQ)            | I.CC_NEQ => emitBr(I.CMPEQ,  I.BEQ)
279      end      end
280      fun copyTmp() = SOME(I.Direct(newReg()))      fun copyTmp() = SOME(I.Direct(C.newReg()))
281      fun fcopyTmp() = SOME(I.FDirect(newFreg()))      fun fcopyTmp() = SOME(I.FDirect(C.newFreg()))
282    in    in
283      case exp      case exp
284       of T.JMP(T.LABEL(LE.LABEL lab), _) => emit(I.BRANCH(I.BR, zeroR, lab))       of T.JMP(T.LABEL(LE.LABEL lab), _) => emit(I.BRANCH(I.BR, zeroR, lab))
# Line 314  Line 312 
312        | T.STORE8(ea, r, region) => let        | T.STORE8(ea, r, region) => let
313            val rs = regAction r            val rs = regAction r
314            val (rd, disp) = eaAction ea            val (rd, disp) = eaAction ea
315            val t1 = newReg()            val t1 = C.newReg()
316            val t2 = newReg()            val t2 = C.newReg()
317            val t3 = newReg()            val t3 = C.newReg()
318          in          in
319            app emit            app emit
320               [I.LOAD{ldOp=I.LDQ_U, r=t1, b=rd, d=disp,mem=mem},               [I.LOAD{ldOp=I.LDQ_U, r=t1, b=rd, d=disp,mem=mem},
# Line 396  Line 394 
394    and opndAction (T.LI value) =    and opndAction (T.LI value) =
395        if value <= 255 andalso value >= 0 then I.IMMop value        if value <= 255 andalso value >= 0 then I.IMMop value
396        else let        else let
397            val tmpR = newReg()            val tmpR = C.newReg()
398          in          in
399            loadImmed (value, zeroR, tmpR);            loadImmed (value, zeroR, tmpR);
400            I.REGop tmpR            I.REGop tmpR
# Line 404  Line 402 
402      | opndAction(T.LI32 value) =      | opndAction(T.LI32 value) =
403        if Word32.<=(value, 0w255) then I.IMMop (Word32.toInt value)        if Word32.<=(value, 0w255) then I.IMMop (Word32.toInt value)
404        else let        else let
405            val tmpR = newReg ()            val tmpR = C.newReg ()
406          in          in
407            loadImmed32 (value, zeroR, tmpR);            loadImmed32 (value, zeroR, tmpR);
408            I.REGop tmpR            I.REGop tmpR
# Line 413  Line 411 
411      | opndAction exp = I.REGop (regAction exp)      | opndAction exp = I.REGop (regAction exp)
412    
413    and reduceOpnd(I.IMMop i) = let    and reduceOpnd(I.IMMop i) = let
414          val rd = newReg()          val rd = C.newReg()
415        in loadImmed(i, zeroR, rd); rd        in loadImmed(i, zeroR, rd); rd
416        end        end
417      | reduceOpnd(I.REGop rd) = rd      | reduceOpnd(I.REGop rd) = rd
# Line 428  Line 426 
426        end        end
427    
428    and regAction (T.REG r) = r    and regAction (T.REG r) = r
429      | regAction exp = regActionRd(exp, newReg())      | regAction exp = regActionRd(exp, C.newReg())
430    
431    and arithOperands(e1, e2, T.LR) = (regAction e1, opndAction e2)    and arithOperands(e1, e2, T.LR) = (regAction e1, opndAction e2)
432      | arithOperands(e1, e2, T.RL) = let      | arithOperands(e1, e2, T.RL) = let
# Line 598  Line 596 
596          end          end
597          (* Load and sign-extend a byte from a  non-aligned address  *)          (* Load and sign-extend a byte from a  non-aligned address  *)
598        | T.LOAD8(exp, region) => let        | T.LOAD8(exp, region) => let
599            val tmpR0 = newReg()            val tmpR0 = C.newReg()
600            val tmpR1 = newReg()            val tmpR1 = C.newReg()
601            val (rt, disp) = eaAction exp            val (rt, disp) = eaAction exp
602          in          in
603            emit(I.LOAD{ldOp=I.LDQ_U, r=tmpR0, b=rt, d=disp, mem=mem});            emit(I.LOAD{ldOp=I.LDQ_U, r=tmpR0, b=rt, d=disp, mem=mem});
# Line 615  Line 613 
613      fun makeEA(r, n) =      fun makeEA(r, n) =
614        if ~32768 <= n andalso n <= 32767 then (r, I.IMMop n)        if ~32768 <= n andalso n <= 32767 then (r, I.IMMop n)
615        else let        else let
616            val tmpR = newReg()            val tmpR = C.newReg()
617            val low = wtoi(Word.andb(itow n, 0w65535))(* unsigned low 16 bits *)            val low = wtoi(Word.andb(itow n, 0w65535))(* unsigned low 16 bits *)
618            val high = n div 65536            val high = n div 65536
619            val (lowsgn, highsgn) =                        (* Sign-extend *)            val (lowsgn, highsgn) =                        (* Sign-extend *)
# Line 635  Line 633 
633    end (* eaAction *)    end (* eaAction *)
634    
635    and fregAction (T.FREG f) = f    and fregAction (T.FREG f) = f
636      | fregAction exp = fregActionFd(exp, newFreg())      | fregAction exp = fregActionFd(exp, C.newFreg())
637    
638    and fregActionFd(exp, fd) = let    and fregActionFd(exp, fd) = let
639      (* macho comment goes here *)      (* macho comment goes here *)
# Line 696  Line 694 
694    
695  (*  (*
696   * $Log: alpha32.sml,v $   * $Log: alpha32.sml,v $
697     * Revision 1.2  1998/05/19 15:40:03  george
698     *   Minor cleanup
699     *
700   * Revision 1.1.1.1  1998/04/08 18:39:00  george   * Revision 1.1.1.1  1998/04/08 18:39:00  george
701   * Version 110.5   * Version 110.5
702   *   *

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