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[smlnj] Annotation of /sml/branches/SMLNJ/src/MLRISC/alpha32/ra/alpha32RegAlloc.sml
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Annotation of /sml/branches/SMLNJ/src/MLRISC/alpha32/ra/alpha32RegAlloc.sml

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1 : monnier 247 (* alpha32RegAlloc.sml --- alpha integer and floating register allocator
2 :     *
3 :     * COPYRIGHT (c) 1996 AT&T Bell Laboratories.
4 :     *
5 :     *)
6 :    
7 :     (* Integer and floating register allocators are a partial application
8 :     * of a curried functor.
9 :     *)
10 :    
11 :    
12 :    
13 :     functor Alpha32RegAlloc(structure I : INSTRUCTIONS where C = Alpha32Cells
14 :     structure P : INSN_PROPERTIES where I = I
15 :     structure F : FLOWGRAPH where I = I
16 :     structure Asm : EMITTER_NEW
17 :     where I = I and P = F.P) :
18 :     sig
19 :     functor IntRa (structure RaUser : RA_USER_PARAMS
20 :     where I = I
21 :     where type B.name = F.B.name) : RA
22 :    
23 :     functor FloatRa (structure RaUser : RA_USER_PARAMS
24 :     where I = I
25 :     where type B.name = F.B.name) : RA
26 :     end =
27 :     struct
28 :     structure C = I.C
29 :     (* liveness analysis for general purpose registers *)
30 :     structure RegLiveness =
31 :     Liveness(structure Flowgraph=F
32 :     structure Instruction=I
33 :     val defUse = P.defUse C.GP
34 :     fun regSet c = #1 (c:Alpha32Cells.cellset)
35 :     fun cellset((_,f),r) = (r,f))
36 :    
37 :    
38 :     (* integer register allocator *)
39 :     functor IntRa =
40 :     RegAllocator
41 :     (structure RaArch = struct
42 :    
43 :     structure InsnProps = P
44 :     structure AsmEmitter = Asm
45 :     structure I = I
46 :     structure Liveness=RegLiveness
47 :     val defUse = P.defUse C.GP
48 :     val firstPseudoR = 32
49 :     val maxPseudoR = Alpha32Cells.maxCell
50 :     val numRegs = Alpha32Cells.numCell Alpha32Cells.GP
51 :     fun regSet c = #1 (c:Alpha32Cells.cellset)
52 :     end)
53 :    
54 :    
55 :    
56 :     (* liveness analysis for floating point registers *)
57 :     structure FregLiveness =
58 :     Liveness(structure Flowgraph=F
59 :     structure Instruction=I
60 :     val defUse = P.defUse C.FP
61 :     fun regSet c = #2 (c:Alpha32Cells.cellset)
62 :     fun cellset((r,_),f) = (r,f))
63 :    
64 :     (* floating register allocator *)
65 :     functor FloatRa =
66 :     RegAllocator
67 :     (structure RaArch = struct
68 :    
69 :     structure InsnProps = P
70 :     structure AsmEmitter = Asm
71 :     structure Liveness=FregLiveness
72 :     structure I = I
73 :    
74 :     val defUse = P.defUse C.FP
75 :     val firstPseudoR = 32
76 :     val maxPseudoR = Alpha32Cells.maxCell
77 :     val numRegs = Alpha32Cells.numCell Alpha32Cells.FP
78 :     fun regSet c = #2 (c:Alpha32Cells.cellset)
79 :     end)
80 :     end
81 :    
82 :    
83 :    
84 :    
85 :     (*
86 :     * $Log: alpha32RegAlloc.sml,v $
87 :     * Revision 1.1.1.1 1999/01/04 21:55:01 george
88 :     * Version 110.12
89 :     *
90 :     * Revision 1.6 1998/10/06 14:07:31 george
91 :     * Flowgraph has been removed from modules that do not need it.
92 :     * Changes to compiler/CodeGen/*/*{MLTree,CG}.sml necessary.
93 :     * [leunga]
94 :     *
95 :     * Revision 1.5 1998/09/30 19:34:39 dbm
96 :     * fixing sharing/defspec conflict
97 :     *
98 :     * Revision 1.4 1998/07/25 03:08:13 george
99 :     * added to support block names in MLRISC
100 :     *
101 :     * Revision 1.3 1998/05/25 15:10:49 george
102 :     * Fixed RCS keywords
103 :     *
104 :     *)

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