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[smlnj] Diff of /sml/branches/SMLNJ/src/MLRISC/hppa/emit/hppaAsm.sml
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Diff of /sml/branches/SMLNJ/src/MLRISC/hppa/emit/hppaAsm.sml

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revision 410, Fri Sep 3 00:25:03 1999 UTC revision 411, Fri Sep 3 00:25:03 1999 UTC
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1  (* hppaAsm.sml  (*
2   *   * This file was automatically generated by MDGen
3   * COPYRIGHT (c) 1996 Bell Laboratories.   * from the machine description file "hppa/hppa.md".
  *  
4   *)   *)
5    
6  functor HppaAsmEmitter  
7    (structure Instr : HPPAINSTR  functor HppaAsmEmitter(structure Instr : HPPAINSTR
8     structure PseudoOps : PSEUDO_OPS                         structure Stream : INSTRUCTION_STREAM
9     structure Shuffle : HPPASHUFFLE where I = Instr) : EMITTER_NEW =                         structure Shuffle : HPPASHUFFLE
10                              where I = Instr
11                          ) : INSTRUCTION_EMITTER =
12  struct  struct
13    structure I = Instr    structure I = Instr
14    structure C = I.C    structure C = I.C
15    structure P = PseudoOps     structure S  = Stream
16       structure P  = S.P
17    structure LE = LabelExp    structure LE = LabelExp
18    structure Constant = I.Constant    structure Constant = I.Constant
   structure Region = I.Region  
   
   fun ms n = if n<0 then ("-"^ Int.toString (~n)) else Int.toString n  
   
   fun error msg = MLRiscErrorMsg.impossible ("HppaAsEmitter." ^ msg)  
19    
20    fun emit s = TextIO.output(!AsmStream.asmOutStream,s)     fun error msg = MLRiscErrorMsg.error("HppaAsm",msg)
   
   fun defineLabel(lab) =     emit(Label.nameOf lab ^ "\n")  
   
   fun comment msg = emit ("\t/* " ^ msg ^ " */")  
   fun region r = comment(Region.toString r)  
   fun pseudoOp pOp = emit(P.toString pOp)  
   fun init size = (comment ("Code Size = " ^ ms size); emit"\n")  
21    
22    fun emitInstr(instr,regmap) = let     fun makeStream() =
23      fun rmap r          = Intmap.map regmap r handle _ => r     let val stream = !AsmStream.asmOutStream
24      fun eReg r          = emit ("%r" ^ ms(rmap r))         fun emit s = TextIO.output(stream,s)
25      fun eFreg f         = emit ("%f" ^ ms(rmap f))         fun nl() = emit "\n"
     fun emitCreg c      = emit ("%f" ^ ms c)  
     fun eLabel lab      = emit (Label.nameOf lab)  
26      fun comma()         = emit ", "      fun comma()         = emit ", "
27      fun tab()           = emit "\t"      fun tab()           = emit "\t"
28      fun newline ()      = emit "\n"         fun ms n = if n<0 then "-"^Int.toString(~n)
29                      else Int.toString n
30           fun emit_label lab = emit(Label.nameOf lab)
31           fun emit_labexp le = emit(LabelExp.toString le)
32           fun emit_const c = emit(Constant.toString c)
33           fun emit_int i = emit(ms i)
34      fun paren f         = (emit "("; f(); emit ")")      fun paren f         = (emit "("; f(); emit ")")
35      fun prList l = let         fun defineLabel lab = emit(Label.nameOf lab^":\n")
36        fun pr [] = emit "]"         fun entryLabel lab = defineLabel lab
37          | pr [r] = (eReg r; pr [])         fun comment msg = emit("\t/* " ^ msg ^ " */")
38          | pr (r::rs) = (eReg r; emit ","; pr rs)         fun annotation a = (comment(Annotations.toString a); nl())
39      in emit "["; pr l         fun blockName b = (comment(S.B.toString b); nl())
40      end         fun emit_region mem = comment(I.Region.toString mem)
41      fun cond I.EQ  = "="         fun pseudoOp pOp = emit(P.toString pOp)
42        | cond I.LT  = "<"         fun init size = (comment("Code Size = " ^ ms size); nl())
43        | cond I.LE  = "<="         fun doNothing _ = ()
44        | cond I.LTU = "<<"         fun emitter regmap =
45        | cond I.LEU = "<<="         let
46        | cond I.NE  = "<>"  
47        | cond I.GE  = ">="     fun emit_CC r = (emit (C.showCC (regmap r)))
48        | cond I.GT  = ">"     and emit_CR r = (emit (C.showCR (regmap r)))
49        | cond I.GTU = ">>"     and emit_GP r = (emit (C.showGP (regmap r)))
50        | cond I.GEU = ">>="     and emit_FP r = (emit (C.showFP (regmap r)))
51    
52      fun fcond I.?    = "?"     fun asm_cmplt (I.ADDR) = ""
53        | fcond I.!<=> = "!<=>"       | asm_cmplt (I.ADDR_S) = ",s"
54        | fcond I.==   = "=="       | asm_cmplt (I.ADDR_M) = ",m"
55        | fcond I.?=   = "?="       | asm_cmplt (I.ADDR_SM) = ",sm"
56        | fcond I.!<>  = "!<>"     and emit_cmplt x = (emit (asm_cmplt x))
57        | fcond I.!?>= = "!?>="     and asm_store (I.STW) = "stw"
58        | fcond I.<    = "<"       | asm_store (I.STH) = "sth"
59        | fcond I.?<   = "?<"       | asm_store (I.STB) = "stb"
60        | fcond I.!>=  = "!>="     and emit_store x = (emit (asm_store x))
61        | fcond I.!?>  = "!?>"     and asm_fcond (I.False_) = "false?"
62        | fcond I.<=   = "<="       | asm_fcond (I.False) = "false"
63        | fcond I.?<=  = "?<+"       | asm_fcond (I.?) = "?"
64        | fcond I.!>   = "!>"       | asm_fcond (I.!<=>) = "!<=>"
65        | fcond I.!?<= = "!?<="       | asm_fcond (I.==) = "=="
66        | fcond I.>    = ">"       | asm_fcond (I.EQT) = "=T"
67        | fcond I.?>   = "?>"       | asm_fcond (I.?=) = "?="
68        | fcond I.!<=  = "!<="       | asm_fcond (I.!<>) = "!<>"
69        | fcond I.!?<  = "!?<"       | asm_fcond (I.!?>=) = "!?>="
70        | fcond I.>=   = ">="       | asm_fcond (I.<) = "<"
71        | fcond I.?>=  = "?>="       | asm_fcond (I.?<) = "?<"
72        | fcond I.!<   = "!<"       | asm_fcond (I.!>=) = "!>="
73        | fcond I.!?=  = "!?="       | asm_fcond (I.!?>) = "!?>"
74        | fcond I.<>   = "<>"       | asm_fcond (I.<=) = "<="
75        | fcond I.!=   = "!="       | asm_fcond (I.?<=) = "?<="
76        | fcond I.!?   = "!?"       | asm_fcond (I.!>) = "!>"
77        | fcond I.<=>  = "<=>"       | asm_fcond (I.!?<=) = "!?<="
78         | asm_fcond (I.>) = ">"
79      fun emitFieldSel fs =       | asm_fcond (I.?>) = "?>"
80        emit(case fs       | asm_fcond (I.!<=) = "!<="
81             of I.F => "F'"       | asm_fcond (I.!?<) = "!?<"
82              | I.T => ""       | asm_fcond (I.>=) = ">="
83              | I.P => "P'"       | asm_fcond (I.?>=) = "?>="
84              | _ => error "emitFieldSel")       | asm_fcond (I.!<) = "!<"
85         | asm_fcond (I.!?=) = "!?="
86      fun emitHiFieldSel fs =       | asm_fcond (I.<>) = "<>"
87        emit(case fs       | asm_fcond (I.!=) = "!="
88             of I.F => "L'"       | asm_fcond (I.NET) = "!=T"
89              | I.S => "LS'"       | asm_fcond (I.!?) = "!?"
90              | I.D => "LD'"       | asm_fcond (I.<=>) = "<=>"
91              | I.R => "LR'"       | asm_fcond (I.True_) = "true?"
92              | I.T => "LT'"       | asm_fcond (I.True) = "true"
93              | I.P => "LP'")     and emit_fcond x = (emit (asm_fcond x))
94       and asm_floadx (I.FLDDX) = "flddx"
95      fun emitLoFieldSel fs =       | asm_floadx (I.FLDDX_S) = "flddx,s"
96        emit(case fs       | asm_floadx (I.FLDDX_M) = "flddx,m"
97             of I.F => "R'"       | asm_floadx (I.FLDDX_SM) = "flddx,sm"
98              | I.S => "RS'"       | asm_floadx (I.FLDWX) = "fldwx"
99              | I.D => "RD'"       | asm_floadx (I.FLDWX_S) = "fldwx,s"
100              | I.R => "RR'"       | asm_floadx (I.FLDWX_M) = "fldwx,m"
101              | I.T => "RT'"       | asm_floadx (I.FLDWX_SM) = "fldwx,sm"
102              | I.P => "RP'")     and emit_floadx x = (emit (asm_floadx x))
103       and asm_fstorex (I.FSTDX) = "fstdx"
104      fun emitLExp lexp = emit(LabelExp.toString lexp)       | asm_fstorex (I.FSTDX_S) = "fstdx,s"
105      fun eOperand(I.IMMED  i) = emit (ms i)       | asm_fstorex (I.FSTDX_M) = "fstdx,m"
106        | eOperand(I.LabExp(lexp, fs)) = (emitFieldSel fs; emitLExp lexp)       | asm_fstorex (I.FSTDX_SM) = "fstdx,sm"
107        | eOperand(I.HILabExp(lexp, fs)) = (emitHiFieldSel fs; emitLExp lexp)       | asm_fstorex (I.FSTWX) = "fstwx"
108        | eOperand(I.LOLabExp(lexp, fs)) = (emitLoFieldSel fs; emitLExp lexp)       | asm_fstorex (I.FSTWX_S) = "fstwx,s"
109        | eOperand(I.ConstOp c) = emit(Constant.toString c)       | asm_fstorex (I.FSTWX_M) = "fstwx,m"
110         | asm_fstorex (I.FSTWX_SM) = "fstwx,sm"
111      fun store(st, b, d, r, mem) =     and emit_fstorex x = (emit (asm_fstorex x))
112        (emit st; eReg r; comma(); eOperand d; paren(fn () => eReg b); region mem)     and asm_fcnv (I.FCNVFF_SD) = "fcnvff,sgl,dbl"
113      fun fstore(fst, b, d, r, mem) =       | asm_fcnv (I.FCNVFF_SQ) = "fcnvff,sgl,quad"
114        (emit fst; eFreg r; comma(); emit(ms d); paren(fn () => eReg b);       | asm_fcnv (I.FCNVFF_DS) = "fcnvff,dbl,sgl"
115         region mem)       | asm_fcnv (I.FCNVFF_DQ) = "fcnvff,dbl,quad"
116      fun fstorex(fstx, b, x, r, mem) =       | asm_fcnv (I.FCNVFF_QS) = "fcnvff,quad,sgl"
117        (emit fstx; eFreg r; eReg x; paren(fn () => eReg b); region mem)       | asm_fcnv (I.FCNVFF_QD) = "fcnvff,quad,dbl"
118      fun loadx(ld, r1, r2, t, mem) =       | asm_fcnv (I.FCNVXF_S) = "fcnvxf,,sgl"
119        (emit ld; eReg r2; paren(fn () => eReg r1); comma(); eReg t; region mem)       | asm_fcnv (I.FCNVXF_D) = "fcnvxf,,dbl"
120      fun floadx(flx, b, x, t, mem) =       | asm_fcnv (I.FCNVXF_Q) = "fcnvxf,,quad"
121        (emit flx; eReg x; paren(fn () => eReg b); comma(); eFreg t; region mem)       | asm_fcnv (I.FCNVFX_S) = "fcnvfx,sgl,"
122      fun arith(a, r1, r2, t) =       | asm_fcnv (I.FCNVFX_D) = "fcnvfx,dbl,"
123        (emit a; eReg r1; comma(); eReg r2; comma(); eReg t)       | asm_fcnv (I.FCNVFX_Q) = "fcnvfx,quad,"
124      fun loadi(ld, i, r, t, mem) =       | asm_fcnv (I.FCNVFXT_S) = "fcnvfxt,sgl,"
125        (emit ld; eOperand i; paren(fn () => eReg r); comma(); eReg t; region mem)       | asm_fcnv (I.FCNVFXT_D) = "fcnvfxt,dbl,"
126      fun fload(fl, b, d, t, mem) =       | asm_fcnv (I.FCNVFXT_Q) = "fcnvfxt,quad,"
127        (emit fl; emit(ms d); paren(fn () => eReg b); comma(); eFreg t; region mem)     and emit_fcnv x = (emit (asm_fcnv x))
128      fun arithi(ai, i, r ,t) =     and asm_arithi (I.ADDI) = "addi"
129        (emit ai; eOperand i; comma(); eReg r; comma(); eReg t)       | asm_arithi (I.ADDIO) = "addio"
130      fun cmp{cc, r1, r2, t} = arith("\tCOMCLR," ^ cond cc ^ "\t", r1, r2, t)       | asm_arithi (I.ADDIL) = "addil"
131      fun shiftv(sv, r, len, t) =       | asm_arithi (I.SUBI) = "subi"
132        (emit sv; eReg r; comma(); emit(ms len); comma(); eReg t)       | asm_arithi (I.SUBIO) = "subio"
133      fun shift(s, r, p, len, t) =     and emit_arithi x = (emit (asm_arithi x))
134        (emit s; eReg r; comma();     and asm_fload (I.FLDDS) = "fldds"
135         emit(ms p); comma();       | asm_fload (I.FLDWS) = "fldws"
136         emit(ms len); comma(); eReg t)     and emit_fload x = (emit (asm_fload x))
137      fun emitCmp I.COMBT  = emit "\tCOMBT,"     and asm_fmt (I.SGL) = "sgl"
138        | emitCmp I.COMBF  = emit "\tCOMBF,"       | asm_fmt (I.DBL) = "dbl"
139      fun emitCmpi I.COMIBT = emit "\tCOMIBT,"       | asm_fmt (I.QUAD) = "quad"
140        | emitCmpi I.COMIBF = emit "\tCOMIBF,"     and emit_fmt x = (emit (asm_fmt x))
141      fun nullify true  = emit ",n"     and asm_bitcond (I.BSET) = "<"
142        | nullify false = ()       | asm_bitcond (I.BCLR) = ">="
143      fun bcond{cmp, bc, r1, r2, t, f, n} =     and emit_bitcond x = (emit (asm_bitcond x))
144        (emitCmp cmp;  emit (cond bc); nullify n; emit "\t";     and asm_cmpi (I.COMIBT) = "comibt"
145         eReg r1; comma(); eReg r2; comma(); eLabel t;       | asm_cmpi (I.COMIBF) = "comibf"
146         emit "\n\tNOP" )     and emit_cmpi x = (emit (asm_cmpi x))
147      fun bcondi{cmpi, bc, i, r2, t, f, n} =     and asm_loadi (I.LDW) = "ldw"
148        (emitCmpi cmpi; emit (cond bc); nullify n; emit "\t";       | asm_loadi (I.LDH) = "ldh"
149         emit(ms i); comma(); eReg r2; comma(); eLabel t;       | asm_loadi (I.LDB) = "ldb"
150         emit "\n\tNOP")     and emit_loadi x = (emit (asm_loadi x))
151       and asm_cmp (I.COMBT) = "combt"
152      fun farith{fa, r1, r2, t} = let       | asm_cmp (I.COMBF) = "combf"
153        val oper = case fa of I.FADD => "\tFADD\t" | I.FSUB => "\tFSUB\t"     and emit_cmp x = (emit (asm_cmp x))
154                            | I.FDIV => "\tFDIV\t" | I.FMPY => "\tFMPY\t"     and asm_farith (I.FADD_S) = "fadd,sgl"
155                            | I.XMPYU => "\tXMPYU\t"       | asm_farith (I.FADD_D) = "fadd,dbl"
156      in emit oper; eFreg r1; comma(); eFreg r2; comma(); eFreg t       | asm_farith (I.FADD_Q) = "fadd,quad"
157      end       | asm_farith (I.FSUB_S) = "fsub,sgl"
158         | asm_farith (I.FSUB_D) = "fsub,dbl"
159      fun funary(fu, f, t) = (emit fu; eFreg f; comma(); eFreg t)       | asm_farith (I.FSUB_Q) = "fsub,quad"
160    in       | asm_farith (I.FMPY_S) = "fmpy,sgl"
161      case instr       | asm_farith (I.FMPY_D) = "fmpy,dbl"
162       of I.STORE{st=I.STW, b, d, r, mem} => store("\tSTW\t", b, d, r, mem)       | asm_farith (I.FMPY_Q) = "fmpy,quad"
163        | I.STORE{st=I.STH, b, d, r, mem} => store("\tSTH\t", b, d, r, mem)       | asm_farith (I.FDIV_S) = "fdiv,sgl"
164        | I.STORE{st=I.STB, b, d, r, mem} => store("\tSTB\t", b, d, r, mem)       | asm_farith (I.FDIV_D) = "fdiv,dbl"
165         | asm_farith (I.FDIV_Q) = "fdiv,quad"
166        | I.LOAD{l=I.LDWX, r1, r2, t, mem}=> loadx("\tLDWX\t", r1, r2, t, mem)       | asm_farith (I.XMPYU) = "xmpyu"
167        | I.LOAD{l=I.LDHX, r1, r2, t, mem}=> loadx("\tLDHX\t", r1, r2, t, mem)     and emit_farith x = (emit (asm_farith x))
168        | I.LOAD{l=I.LDBX, r1, r2, t, mem}=> loadx("\tLDBX\t", r1, r2, t, mem)     and asm_bcond (I.EQ) = "="
169        | I.ARITH{a=I.ADD,  r1, r2, t}    => arith("\tADD\t", r1, r2, t)       | asm_bcond (I.LT) = "<"
170        | I.ARITH{a=I.ADDO,  r1, r2, t}   => arith("\tADDO\t", r1, r2, t)       | asm_bcond (I.LE) = "<="
171        | I.ARITH{a=I.SH1ADD,  r1, r2, t} => arith("\tSH1ADD\t", r1, r2, t)       | asm_bcond (I.LTU) = "<<"
172        | I.ARITH{a=I.SH1ADDO, r1, r2, t} => arith("\tSH1ADDO\t", r1, r2, t)       | asm_bcond (I.LEU) = "<<="
173        | I.ARITH{a=I.SUB,  r1, r2, t}    => arith("\tSUB\t", r1, r2, t)       | asm_bcond (I.NE) = "<>"
174        | I.ARITH{a=I.SUBO,  r1, r2, t}   => arith("\tSUBO\t", r1, r2, t)       | asm_bcond (I.GE) = ">="
175        | I.ARITH{a=I.OR,  r1, r2, t}     => arith("\tOR\t", r1, r2, t)       | asm_bcond (I.GT) = ">"
176        | I.ARITH{a=I.XOR,  r1, r2, t}    => arith("\tXOR\t", r1, r2, t)       | asm_bcond (I.GTU) = ">>"
177        | I.ARITH{a=I.AND,  r1, r2, t}    => arith("\tAND\t", r1, r2, t)       | asm_bcond (I.GEU) = ">>="
178       and emit_bcond x = (emit (asm_bcond x))
179        | I.LOADI{li=I.LDB, i, r, t, mem} => loadi("\tLDB\t", i, r, t, mem)     and asm_shift (I.EXTRU) = "extru"
180        | I.LOADI{li=I.LDH,  i, r, t,mem} => loadi("\tLDH\t", i, r, t, mem)       | asm_shift (I.EXTRS) = "extrs"
181        | I.LOADI{li=I.LDW, i, r, t, mem} => loadi("\tLDW\t", i, r, t, mem)       | asm_shift (I.ZDEP) = "zdep"
182        | I.ARITHI{ai=I.ADDI, i, r, t}    => arithi("\tADDI\t", i, r, t)     and emit_shift x = (emit (asm_shift x))
183        | I.ARITHI{ai=I.ADDIO, i, r, t}   => arithi("\tADDIO\t", i, r, t)     and asm_arith (I.ADD) = "add"
184        | I.ARITHI{ai=I.ADDIL, i, r, t}   => arithi("\tADDIL\t", i, r, t)       | asm_arith (I.ADDL) = "addl"
185        | I.ARITHI{ai=I.SUBI, i, r, t}    => arithi("\tSUBI\t", i, r, t)       | asm_arith (I.ADDO) = "addo"
186        | I.ARITHI{ai=I.SUBIO, i, r, t}   => arithi("\tSUBIO\t", i, r, t)       | asm_arith (I.SH1ADD) = "sh1add"
187         | asm_arith (I.SH1ADDL) = "sh1addl"
188        | I.COMCLR arg                    => cmp arg       | asm_arith (I.SH1ADDO) = "sh1addo"
189         | asm_arith (I.SH2ADD) = "sh2add"
190        | I.SHIFTV{sv=I.VEXTRU, r, len, t}=> shiftv("\tVEXTRU\t",  r, len, t)       | asm_arith (I.SH2ADDL) = "sh2addl"
191        | I.SHIFTV{sv=I.VEXTRS, r, len, t}=> shiftv("\tVEXTRS\t",  r, len, t)       | asm_arith (I.SH2ADDO) = "sh2addo"
192        | I.SHIFTV{sv=I.ZVDEP, r, len, t} => shiftv("\tZVDEP\t", r, len, t)       | asm_arith (I.SH3ADD) = "sh3add"
193         | asm_arith (I.SH3ADDL) = "sh3addl"
194        | I.SHIFT{s=I.EXTRU, r, p, len, t}=> shift("\tEXTRU\t", r, p, len, t)       | asm_arith (I.SH3ADDO) = "sh3addo"
195        | I.SHIFT{s=I.EXTRS, r, p, len, t}=> shift("\tEXTRS\t", r, p, len, t)       | asm_arith (I.SUB) = "sub"
196        | I.SHIFT{s=I.ZDEP, r, p, len, t} => shift("\tZDEP\t", r, p, len, t)       | asm_arith (I.SUBO) = "subo"
197         | asm_arith (I.OR) = "or"
198        | I.BCOND arg                     => bcond arg       | asm_arith (I.XOR) = "xor"
199        | I.BCONDI arg                    => bcondi arg       | asm_arith (I.AND) = "and"
200        | I.B{lab,n}                      => (emit "\tB"; nullify n;       | asm_arith (I.ANDCM) = "andcm"
201                                              emit "\t"; eLabel lab;     and emit_arith x = (emit (asm_arith x))
202                                              emit "\n\tNOP" )     and asm_load (I.LDWX) = "ldwx"
203        | I.FBRANCH{cc,f1,f2,t,n,...} =>       | asm_load (I.LDWX_S) = "ldwx,s"
204            (emit ("\tFCMP," ^ fcond cc ^"\t"); eFreg f1; comma(); eFreg f2;       | asm_load (I.LDWX_M) = "ldwx,m"
205             emit "\n\tFTEST\n";       | asm_load (I.LDWX_SM) = "ldwx,sm"
206             emit "\tB"; nullify n; emit "\t"; eLabel t; emit "\n\tNOP")       | asm_load (I.LDHX) = "ldhx"
207        | I.BLE{d, sr, b, t, ...} =>       | asm_load (I.LDHX_S) = "ldhx,s"
208            (emit "\tBLE\t"; eOperand d;       | asm_load (I.LDHX_M) = "ldhx,m"
209             paren(fn () => (emit(ms sr); comma(); eReg b));       | asm_load (I.LDHX_SM) = "ldhx,sm"
210             emit "\n\tCOPY %r31,"; eReg t)       | asm_load (I.LDBX) = "ldbx"
211        | I.BL{x=I.LabExp(LE.LABEL lab, fs), t, n, ...} =>       | asm_load (I.LDBX_M) = "ldbx,m"
212            (emit "\tBL"; nullify n;     and emit_load x = (emit (asm_load x))
213             emit "\t"; emitFieldSel fs; eLabel lab; comma(); eReg t;     and asm_shiftv (I.VEXTRU) = "vextru"
214             emit "\n\tNOP" )       | asm_shiftv (I.VEXTRS) = "vextrs"
215        | I.BL _ => error "emitInstr:bl"       | asm_shiftv (I.ZVDEP) = "zvdep"
216        | I.BV{x, b, n, ...} =>     and emit_shiftv x = (emit (asm_shiftv x))
217            (emit "\tBV"; nullify n; emit "\t"; eReg x; paren(fn () => eReg b);     and asm_funary (I.FCPY_S) = "fcpy,sgl"
218             emit "\n\tNOP" )       | asm_funary (I.FCPY_D) = "fcpy,dbl"
219        | I.BLR{x, t, n, labs, ...} =>       | asm_funary (I.FCPY_Q) = "fcpy,quad"
220            (emit "\tBLR"; nullify n; emit "\t"; eReg x; comma(); eReg t;       | asm_funary (I.FABS_S) = "fabs,sgl"
221             emit "\n\tNOP\n";       | asm_funary (I.FABS_D) = "fabs,dbl"
222             app (fn l => (emit "\tB,n\t"; eLabel l; emit "\n\tNOP\n")) labs       | asm_funary (I.FABS_Q) = "fabs,quad"
223            )       | asm_funary (I.FSQRT_S) = "fsqrt,sgl"
224        | I.LDIL{i, t} => (emit "\tLDIL\t"; eOperand i; comma(); eReg t)       | asm_funary (I.FSQRT_D) = "fsqrt,dbl"
225         | asm_funary (I.FSQRT_Q) = "fsqrt,quad"
226         | asm_funary (I.FRND_S) = "frnd,sgl"
227         | asm_funary (I.FRND_D) = "frnd,dbl"
228         | asm_funary (I.FRND_Q) = "frnd,quad"
229       and emit_funary x = (emit (asm_funary x))
230       and emit_operand (I.IMMED int) = (emit_int int)
231         | emit_operand (I.LabExp(labexp, field_selector)) = (emit_labexp labexp)
232         | emit_operand (I.HILabExp(labexp, field_selector)) = (emit_labexp labexp)
233         | emit_operand (I.LOLabExp(labexp, field_selector)) = (emit_labexp labexp)
234         | emit_operand (I.ConstOp const) = (emit_const const)
235       and asm_fstore (I.FSTDS) = "fstds"
236         | asm_fstore (I.FSTWS) = "fstws"
237       and emit_fstore x = (emit (asm_fstore x))
238    
239       fun emit_n false = ()
240         | emit_n true = (emit ",n")
241    
242       fun emit_nop false = ()
243         | emit_nop true = (emit "\n\tnop")
244    
245       fun emitInstr instr =
246           ((tab ());
247    
248           (
249            case instr of
250            I.LOADI{li, r, i, t, mem} =>
251            ((emit_loadi li);
252            (emit "\t");
253            (emit_operand i);
254            (emit "(");
255            (emit_GP r);
256            (emit "), ");
257            (emit_GP t);
258            (emit_region mem))
259          | I.LOAD{l, r1, r2, t, mem} =>
260            ((emit_load l);
261            (emit "\t");
262            (emit_GP r2);
263            (emit "(");
264            (emit_GP r1);
265            (emit "), ");
266            (emit_GP t);
267            (emit_region mem))
268          | I.STORE{st, b, d, r, mem} =>
269            ((emit_store st);
270            (emit "\t");
271            (emit_GP r);
272            (emit ", ");
273            (emit_operand d);
274            (emit "(");
275            (emit_GP b);
276            (emit ")");
277            (emit_region mem))
278          | I.ARITH{a, r1, r2, t} =>
279            ((emit_arith a);
280            (emit "\t");
281            (emit_GP r1);
282            (emit ", ");
283            (emit_GP r2);
284            (emit ", ");
285            (emit_GP t))
286          | I.ARITHI{ai, i, r, t} =>
287            ((emit_arithi ai);
288            (emit "\t");
289            (emit_operand i);
290            (emit ", ");
291            (emit_GP r);
292            (emit ", ");
293            (emit_GP t))
294          | I.COMCLR_LDO{cc, r1, r2, t1, i, b, t2} =>
295            ((emit "comclr,");
296            (emit_bcond cc);
297            (emit "\t");
298            (emit_GP r1);
299            (emit ", ");
300            (emit_GP r2);
301            (emit ", ");
302            (emit_GP t1);
303            (emit "\n\tldo\t");
304            (emit_int i);
305            (emit "(");
306            (emit_GP b);
307            (emit "), ");
308            (emit_GP t2))
309          | I.SHIFTV{sv, r, len, t} =>
310            ((emit_shiftv sv);
311            (emit "\t");
312            (emit_GP r);
313            (emit ", ");
314            (emit_int len);
315            (emit ", ");
316            (emit_GP t))
317          | I.SHIFT{s, r, p, len, t} =>
318            ((emit_shift s);
319            (emit "\t");
320            (emit_GP r);
321            (emit ", ");
322            (emit_int p);
323            (emit ", ");
324            (emit_int len);
325            (emit ", ");
326            (emit_GP t))
327          | I.BCOND{cmp, bc, r1, r2, n, nop, t, f} =>
328            ((emit_cmp cmp);
329            (emit ",");
330            (emit_bcond bc);
331            (emit_n n);
332            (emit "\t");
333            (emit_GP r1);
334            (emit ", ");
335            (emit_GP r2);
336            (emit ", ");
337            (emit_label t);
338            (emit_nop nop))
339          | I.BCONDI{cmpi, bc, i, r2, n, nop, t, f} =>
340            ((emit_cmpi cmpi);
341            (emit ",");
342            (emit_bcond bc);
343            (emit_n n);
344            (emit "\t");
345            (emit_int i);
346            (emit ", ");
347            (emit_GP r2);
348            (emit ", ");
349            (emit_label t);
350            (emit_nop nop))
351          | I.BB{bc, r, p, n, nop, t, f} =>
352            ((emit "bb,");
353            (emit_bitcond bc);
354            (emit_n n);
355            (emit "\t");
356            (emit_GP r);
357            (emit ", ");
358            (emit_int p);
359            (emit ", ");
360            (emit_label t);
361            (emit_nop nop))
362          | I.B{lab, n} =>
363            ((emit "b");
364            (emit_n n);
365            (emit "\t");
366            (emit_label lab))
367          | I.BV{x, b, labs, n} =>
368            ((emit "bv");
369            (emit_n n);
370            (emit "\t");
371            (emit_GP x);
372            (emit "(");
373            (emit_GP b);
374            (emit ")"))
375          | I.BLR{x, t, labs, n} =>
376            ((emit "blr");
377            (emit_n n);
378            (emit "\t");
379            (emit_GP x);
380            (emit "(");
381            (emit_GP t);
382            (emit ")"))
383          | I.BL{x, t, defs, uses, n} =>
384            ((emit "bl");
385            (emit_n n);
386            (emit "\t");
387            (emit_operand x);
388            (emit "), ");
389            (emit_GP t))
390          | I.BLE{d, b, sr, t, defs, uses, mem} =>
391            ((emit "ble\t");
392            (emit_operand d);
393            (emit "(");
394            (emit_int sr);
395            (emit ",");
396            (emit_GP b);
397            (emit ")");
398            (emit_region mem))
399          | I.LDIL{i, t} =>
400            ((emit "ldil\t");
401            (emit_operand i);
402            (emit ", ");
403            (emit_GP t))
404        | I.LDO{i,b,t} =>        | I.LDO{i,b,t} =>
405            (emit "\tLDO\t";  eOperand i; paren(fn () => eReg b);          ((emit "ldo\t");
406             comma(); eReg t)          (emit_operand i);
407        | I.MTCTL{r,t} => (emit "\tMTCTL\t"; eReg r; emitCreg t)          (emit "(");
408            (emit_GP b);
409            (emit "), ");
410            (emit_GP t))
411          | I.MTCTL{r, t} =>
412            ((emit "mtctl\t");
413            (emit_GP r);
414            (emit ", ");
415            (emit_CR t))
416        | I.FSTORE{fst, b, d, r, mem} =>        | I.FSTORE{fst, b, d, r, mem} =>
417            (case fst          ((emit_fstore fst);
418              of I.FSTDS => fstore("\tFSTDS\t", b, d, r, mem)          (emit "\t");
419               | I.FSTWS => fstore("\tFSTWS\t", b, d, r, mem)          (emit_int d);
420            (*esac*))          (emit "(");
421            (emit_GP b);
422            (emit "), ");
423            (emit_FP r);
424            (emit_region mem))
425        | I.FSTOREX{fstx, b, x, r, mem} =>        | I.FSTOREX{fstx, b, x, r, mem} =>
426            (case fstx          ((emit_fstorex fstx);
427              of I.FSTDX => fstorex("\tFSTDX\t", b, x, r, mem)          (emit "\t");
428               | I.FSTWX => fstorex("\tFSTWX\t", b, x, r, mem)          (emit_GP x);
429            (*esac*))          (emit "(");
430        | I.FLOAD{fl=I.FLDDS, b, d, t, mem} => fload("\tFLDDS\t", b, d, t, mem)          (emit_GP b);
431        | I.FLOAD{fl=I.FLDWS, b, d, t, mem} => fload("\tFLDWS\t", b, d, t, mem)          (emit "), ");
432        | I.FLOADX{flx=I.FLDDX, b, x, t, mem} => floadx("\tFLDDX\t", b, x, t, mem)          (emit_FP r);
433        | I.FLOADX{flx=I.FLDWX, b, x, t, mem} => floadx("\tFLDWX\t", b, x, t, mem)          (emit_region mem))
434        | I.FARITH arg => farith arg        | I.FLOAD{fl, b, d, t, mem} =>
435        | I.FUNARY{fu=I.FCPY, f, t} => funary("\tFCPY\t", f, t)          ((emit_fload fl);
436        | I.FUNARY{fu=I.FABS, f, t} => funary("\tFABS\t", f, t)          (emit "\t");
437        | I.FUNARY{fu=I.FCNVXF, f, t} => funary("\tFCNVXF\t", f, t)          (emit_int d);
438        | I.BREAK(i, j) => emit ("\tBREAK(" ^ ms i ^ ", " ^ ms j ^ ")")          (emit "(");
439        | I.NOP => emit "\tNOP"          (emit_GP b);
440        | I.COPY{dst, src, tmp, ...} =>          (emit "), ");
441            app (fn I => (emit "\t"; emitInstr(I, regmap)))          (emit_FP t);
442                (Shuffle.shuffle {regMap=rmap, temp=tmp, dst=dst, src=src})          (emit_region mem))
443        | I.FCOPY{dst, src, tmp, ...} =>        | I.FLOADX{flx, b, x, t, mem} =>
444            app (fn I => (emit "\t"; emitInstr(I, regmap)))          ((emit_floadx flx);
445                (Shuffle.shufflefp {regMap=rmap, temp=tmp, dst=dst, src=src})          (emit "\t");
446        (*esac*);          (emit_GP x);
447      emit "\n"          (emit "(");
448            (emit_GP b);
449            (emit "), ");
450            (emit_FP t);
451            (emit_region mem))
452          | I.FARITH{fa, r1, r2, t} =>
453            ((emit_farith fa);
454            (emit "\t");
455            (emit_FP r1);
456            (emit ", ");
457            (emit_FP r2);
458            (emit ", ");
459            (emit_FP t))
460          | I.FUNARY{fu, f, t} =>
461            ((emit_funary fu);
462            (emit "\t");
463            (emit_FP f);
464            (emit ", ");
465            (emit_FP t))
466          | I.FCNV{fcnv, f, t} =>
467            ((emit_fcnv fcnv);
468            (emit "\t");
469            (emit_FP f);
470            (emit ", ");
471            (emit_FP t))
472          | I.FBRANCH{cc, fmt, f1, f2, t, f, n, long} =>
473            ((emit "fcmp,");
474            (emit_fmt fmt);
475            (emit ",");
476            (emit_fcond cc);
477            (emit "\t");
478            (emit_FP f1);
479            (emit ", ");
480            (emit_FP f2);
481            (emit "\n\tftest\n\tb");
482            (emit_n n);
483            (emit "\t");
484            (emit_label t))
485          | I.BREAK{code1, code2} =>
486            ((emit "break\t");
487            (emit_int code1);
488            (emit ", ");
489            (emit_int code2))
490          | I.NOP => (emit "nop")
491          | I.COPY{dst, src, impl, tmp} => (emitInstrs (Shuffle.shuffle {regmap=regmap, tmp=tmp, src=src, dst=dst}))
492          | I.FCOPY{dst, src, impl, tmp} => (emitInstrs (Shuffle.shufflefp {regmap=regmap, tmp=tmp, src=src, dst=dst}))
493          | I.ANNOTATION{i, a} =>
494            ((emitInstr i);
495            (comment (Annotations.toString a)))
496          | I.GROUP annotation => (comment (Annotations.toString annotation))
497           );
498           (nl ()))
499              and emitInstrs [] = ()
500                | emitInstrs (i::is) =
501               (emitInstr i; app (fn i => (tab(); emitInstr i)) is)
502          in  emitInstr end
503    
504       in  S.STREAM{init=init,
505                    pseudoOp=pseudoOp,
506                    emit=emitter,
507                    finish=doNothing,
508                    defineLabel=defineLabel,
509                    entryLabel=entryLabel,
510                    comment=comment,
511                    exitBlock=doNothing,
512                    blockName=blockName,
513                    annotation=annotation
514                   }
515    end    end
516  end  end
517    
   
 (*  
  * $Log: hppaAsm.sml,v $  
  * Revision 1.6  1998/10/06 14:04:27  george  
  *   The instruction sequence FCMP, FTEST, FBCC is being replaced  
  *   by the composite instruction FBRANCH.  This makes scheduling and  
  *   other tasks easier.  Also, added BLR and BL in the instruction set.  
  *                                                      [leunga]  
  *  
  * Revision 1.5  1998/09/30 19:35:22  dbm  
  * fixing sharing/defspec conflict  
  *  
  * Revision 1.4  1998/07/25 03:08:15  george  
  *   added to support block names in MLRISC  
  *  
  * Revision 1.3  1998/05/25 15:10:53  george  
  *   Fixed RCS keywords  
  *  
  *)  

Legend:
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  Added in v.411

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