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[smlnj] Diff of /sml/branches/SMLNJ/src/MLRISC/hppa/hppa.sml
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Diff of /sml/branches/SMLNJ/src/MLRISC/hppa/hppa.sml

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sml/trunk/src/MLRISC/hppa/hppa.sml revision 16, Wed Mar 11 21:00:04 1998 UTC sml/branches/SMLNJ/src/MLRISC/hppa/hppa.sml revision 167, Sat Nov 7 20:11:41 1998 UTC
# Line 6  Line 6 
6   *   *
7   *)   *)
8  functor Hppa  functor Hppa
9    (structure Flowgen : FLOWGRAPH_GEN    (structure HppaInstr : HPPAINSTR
10     structure HppaInstr : HPPAINSTR     structure HppaMLTree : MLTREE where Region = HppaInstr.Region
11     structure HppaMLTree : MLTREE                                   and Constant = HppaInstr.Constant
12     structure MilliCode : HPPA_MILLICODE     structure Flowgen : FLOWGRAPH_GEN where I = HppaInstr
13     structure LabelComp : LABEL_COMP                                       and T = HppaMLTree
14                                         and B = HppaMLTree.BNames
15       structure MilliCode : HPPA_MILLICODE where I = HppaInstr
16       structure LabelComp : LABEL_COMP where I = HppaInstr
17                                        and T = HppaMLTree
18    (* DBM: sharing/defn conflict:
19       sharing Flowgen.I = MilliCode.I = LabelComp.I = HppaInstr       sharing Flowgen.I = MilliCode.I = LabelComp.I = HppaInstr
20       sharing Flowgen.T = LabelComp.T = HppaMLTree       sharing Flowgen.T = LabelComp.T = HppaMLTree
21       sharing HppaMLTree.Region = HppaInstr.Region       sharing HppaMLTree.Region = HppaInstr.Region
22       sharing HppaMLTree.Constant = HppaInstr.Constant) : MLTREECOMP =       sharing HppaMLTree.Constant = HppaInstr.Constant
23         sharing HppaMLTree.BNames = Flowgen.B
24    *)
25      ) : MLTREECOMP =
26  struct  struct
27    structure I = HppaInstr    structure I = HppaInstr
28    structure F = Flowgen    structure F = Flowgen
# Line 36  Line 43 
43    
44    val itow = Word.fromInt    val itow = Word.fromInt
45    
46      val emitInstr = F.emitInstr
47    val emit = F.emitInstr    val emit = F.emitInstr
48    val ldLabelEA = LC.ldLabelEA emit    val ldLabelEA = LC.ldLabelEA emit
49    val ldLabelOpnd = LC.ldLabelOpnd emit    val ldLabelOpnd = LC.ldLabelOpnd emit
50    
   fun newReg () = C.newReg()  
   fun newFreg() = C.newFreg()  
   
51    datatype ea = DISPea of int * I.operand  | INDXea of int * int    datatype ea = DISPea of int * I.operand  | INDXea of int * int
52    
53    (* integer ranges *)    (* integer ranges *)
# Line 65  Line 70 
70      if im14 n then (emit(I.LDO{i=I.IMMED n, b=0, t=rd}); rd)      if im14 n then (emit(I.LDO{i=I.IMMED n, b=0, t=rd}); rd)
71      else let      else let
72          val (hi, lo) = split n          val (hi, lo) = split n
73          val tmpR = newReg()          val tmpR = C.newReg()
74        in        in
75          emit(I.LDIL{i=I.IMMED hi, t=tmpR});          emit(I.LDIL{i=I.IMMED hi, t=tmpR});
76          emit(I.LDO{i=I.IMMED lo, b=tmpR, t=rd});          emit(I.LDO{i=I.IMMED lo, b=tmpR, t=rd});
77          rd          rd
78        end        end
79    
80    fun loadImmed n = loadImmedRd(n, newReg())    fun loadImmed n = loadImmedRd(n, C.newReg())
81    
82    fun loadWord32Rd(w, rd) = let    fun loadWord32Rd(w, rd) = let
83      val toInt = Word32.toIntX      val toInt = Word32.toIntX
84    in    in
85      if Word32.<(w, 0w8192) then emit(I.LDO{i=I.IMMED(toInt w), b=0, t=rd})      if Word32.<(w, 0w8192) then emit(I.LDO{i=I.IMMED(toInt w), b=0, t=rd})
86      else let      else let
87          val tmpR = newReg()          val tmpR = C.newReg()
88          val hi = Word32.~>>(w, 0w11)          val hi = Word32.~>>(w, 0w11)
89          val lo = Word32.andb(w, 0wx7ff)          val lo = Word32.andb(w, 0wx7ff)
90        in        in
# Line 88  Line 93 
93        end;        end;
94      rd      rd
95    end    end
96    fun loadWord32 w = loadWord32Rd(w, newReg())    fun loadWord32 w = loadWord32Rd(w, C.newReg())
97    
98    fun milliCall(milliFn, exp1, exp2, ord, rd) = let    fun milliCall(milliFn, exp1, exp2, ord, rd) = let
99      val (rs, rt) = orderedRR(exp1, exp2, ord)      val (rs, rt) = orderedRR(exp1, exp2, ord)
# Line 137  Line 142 
142                   if im14 disp then bd                   if im14 disp then bd
143                   else let                   else let
144                       val (hi21, lo11) = split disp                       val (hi21, lo11) = split disp
145                       val tmpR1 = newReg()                       val tmpR1 = C.newReg()
146                       val tmpR2 = newReg()                       val tmpR2 = C.newReg()
147                     in                     in
148                       emit(I.LDIL{i=I.IMMED hi21, t=tmpR1});                       emit(I.LDIL{i=I.IMMED hi21, t=tmpR1});
149                       emit(I.ARITH{a=I.ADD, r1=base, r2=tmpR1, t=tmpR2});                       emit(I.ARITH{a=I.ADD, r1=base, r2=tmpR1, t=tmpR2});
# Line 146  Line 151 
151                     end                     end
152               | DISPea bd => bd               | DISPea bd => bd
153               | INDXea(r1,r2) => let               | INDXea(r1,r2) => let
154                   val t = newReg()                   val t = C.newReg()
155                 in                 in
156                   emit (I.ARITH {a=I.ADD, r1=r1, r2=r2, t=t});                   emit (I.ARITH {a=I.ADD, r1=r1, r2=r2, t=t});
157                   (t, I.IMMED 0)                   (t, I.IMMED 0)
# Line 164  Line 169 
169              else              else
170                emit(I.FSTOREX{fstx=I.FSTDX, b=b, x=loadImmed d, r=r, mem=mem})                emit(I.FSTOREX{fstx=I.FSTDX, b=b, x=loadImmed d, r=r, mem=mem})
171           | DISPea(b, d) => let           | DISPea(b, d) => let
172                val tmpR = newReg()                val tmpR = C.newReg()
173             in             in
174               emit(I.ARITHI{ai=I.ADDI, r=b, i=d, t=tmpR});               emit(I.ARITHI{ai=I.ADDI, r=b, i=d, t=tmpR});
175               emit(I.FSTORE{fst=I.FSTDS, b=tmpR, d=0, r=r, mem=mem})               emit(I.FSTORE{fst=I.FSTDS, b=tmpR, d=0, r=r, mem=mem})
# Line 191  Line 196 
196           | T.NEQ  => emitBranch(I.COMBF, I.EQ,  r1, r2)           | T.NEQ  => emitBranch(I.COMBF, I.EQ,  r1, r2)
197        (*esac*))        (*esac*))
198      end      end
199      fun copyTmp() = SOME(I.Direct(newReg()))      fun copyTmp() = SOME(I.Direct(C.newReg()))
200      fun fcopyTmp() = SOME(I.FDirect(newFreg()))      fun fcopyTmp() = SOME(I.FDirect(C.newFreg()))
201    
202      val reduce={stm=stmAction, rexp=regAction, emit=emit}      val reduce={stm=stmAction, rexp=regAction, emit=emit}
203      val returnPtr = 2      val returnPtr = 2
# Line 294  Line 299 
299             | fcond T.<>   = I.?=             | fcond T.<>   = I.?=
300             | fcond T.?=   = I.<>             | fcond T.?=   = I.<>
301         in         in
302           emit(I.FCMP(fcond cc, f1, f2));           emit(I.FBRANCH{cc=fcond cc,f1=f1,f2=f2,t=lab,f=fallThrough, n=true,
303           emit(I.FTEST);                          long=false});
          emit(I.FBCC{t=lab, f=fallThrough, n=true});  
304           F.defineLabel fallThrough           F.defineLabel fallThrough
305         end         end
306    end    end
# Line 324  Line 328 
328      | ccActionCd(T.LOADCC _, _) = error "ccAction:LOADCC"      | ccActionCd(T.LOADCC _, _) = error "ccAction:LOADCC"
329    
330    and regAction(T.REG r) = r    and regAction(T.REG r) = r
331      | regAction exp = regActionRd(exp, newReg())      | regAction exp = regActionRd(exp, C.newReg())
332    
333    and regActionRd(exp, rd) = let    and regActionRd(exp, rd) = let
334      datatype opnd = REG of int | OPND of I.operand      datatype opnd = REG of int | OPND of I.operand
# Line 377  Line 381 
381                end                end
382            | f(exp1, exp2, order) = let            | f(exp1, exp2, order) = let
383                val (r1, r2) = orderedRR(exp1, exp2, order)                val (r1, r2) = orderedRR(exp1, exp2, order)
384                val tmp = newReg()                val tmp = C.newReg()
385              in              in
386                emit(I.ARITHI{ai=I.SUBI, i=I.IMMED 31, r=r2, t=tmp});                emit(I.ARITHI{ai=I.SUBI, i=I.IMMED 31, r=r2, t=tmp});
387                emit(I.MTCTL{r=tmp, t=11});                emit(I.MTCTL{r=tmp, t=11});
# Line 446  Line 450 
450    end (* regActionRd *)    end (* regActionRd *)
451    
452    and fregAction (T.FREG f) = f    and fregAction (T.FREG f) = f
453      | fregAction exp = fregActionFd(exp, newFreg())      | fregAction exp = fregActionFd(exp, C.newFreg())
454    
455    and fregActionFd(exp, fd) = let    and fregActionFd(exp, fd) = let
456      fun orderedFarith(exp1, exp2, ord, arithOp) = let      fun orderedFarith(exp1, exp2, ord, arithOp) = let
# Line 469  Line 473 
473                  emit(I.FLOADX{flx=I.FLDDX, b=r, x=loadImmed n, t=fd,                  emit(I.FLOADX{flx=I.FLDDX, b=r, x=loadImmed n, t=fd,
474                                mem=region})                                mem=region})
475             | DISPea(r,d) => let             | DISPea(r,d) => let
476                  val tmpR = newReg()                  val tmpR = C.newReg()
477               in               in
478                 emit(I.ARITHI{ai=I.ADDI, r=r, i=d, t=tmpR});                 emit(I.ARITHI{ai=I.ADDI, r=r, i=d, t=tmpR});
479                 emit(I.FLOADX{flx=I.FLDDX, b=tmpR, x=zeroR, t=fd,mem=region})                 emit(I.FLOADX{flx=I.FLDDX, b=tmpR, x=zeroR, t=fd,mem=region})
# Line 504  Line 508 
508        | mltc(T.ORDERED mlts)     = F.ordered mlts        | mltc(T.ORDERED mlts)     = F.ordered mlts
509        | mltc(T.BEGINCLUSTER)     = F.beginCluster()        | mltc(T.BEGINCLUSTER)     = F.beginCluster()
510        | mltc(T.CODE stms)        = app stmAction stms        | mltc(T.CODE stms)        = app stmAction stms
511          | mltc(T.BLOCK_NAME name)  = F.blockName name
512        | mltc(T.ENDCLUSTER regmap)= F.endCluster regmap        | mltc(T.ENDCLUSTER regmap)= F.endCluster regmap
513        | mltc(T.ESCAPEBLOCK regs) = F.exitBlock (map cc regs)        | mltc(T.ESCAPEBLOCK regs) = F.exitBlock (map cc regs)
514    in mltc mltree    in mltc mltree
# Line 514  Line 519 
519    
520  (*  (*
521   * $Log: hppa.sml,v $   * $Log: hppa.sml,v $
522   * Revision 1.10  1998/02/17 02:49:44  george   * Revision 1.6  1998/09/30 19:35:03  dbm
523   *   Added the nullify bit to all branch instructions -- leunga   * fixing sharing/defspec conflict
524   *   *
525   * Revision 1.9  1998/02/16 13:58:11  george   * Revision 1.5  1998/08/11 14:03:23  george
526   *   A register allocated temp is now associated with parallel COPYs   *   Exposed emitInstr in MLTREECOMP to allow a client to directly
527   *   instead of a dedicated register. The temp is used to break cycles.   *   inject native instructions into the flowgraph.
528   *   *
529   * Revision 1.8  1997/09/29 20:58:26  george   * Revision 1.3  1998/05/25 15:10:52  george
530   *   Propagate region information through instruction set   *   Fixed RCS keywords
531   *   *
 # Revision 1.7  1997/09/17  17:10:12  george  
 #   added support for MLRisc ENTRYLABEL  
 #  
 # Revision 1.6  1997/09/12  10:12:57  george  
 #   provided support for unsigned comparisons in sml/nj checklimit  
 #  
 # Revision 1.5  1997/08/29  11:01:08  george  
 #   MULU is now implemented as millicode instead of floating  
 #   point registers.  
 #  
 # Revision 1.4  1997/07/28  20:04:14  george  
 #   Added support for regions in the MLTree language  
 #  
 # Revision 1.3  1997/07/17  12:26:59  george  
 #   The regmap is now represented as an int map rather than using arrays.  
 #  
 # Revision 1.2  1997/07/10  04:00:03  george  
 #   Added translation for MLTree.ORDERED.  
 #  
 # Revision 1.1.1.1  1997/04/19  18:14:22  george  
 #   Version 109.27  
 #  
532   *)   *)

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