Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Annotation of /sml/branches/SMLNJ/src/MLRISC/instructions/cells.sig
ViewVC logotype

Annotation of /sml/branches/SMLNJ/src/MLRISC/instructions/cells.sig

Parent Directory Parent Directory | Revision Log Revision Log


Revision 245 - (view) (download) (as text)

1 : monnier 245 (* cells.sig
2 :     *
3 :     * COPYRIGHT (c) 1995 AT&T Bell Laboratories.
4 :     *
5 :     * CELLS - describes storage units on the machine, such as
6 :     * dedicated and general registers, memory ...
7 :     *
8 :     * This file acts as a bridge between MLRISC and the machine
9 :     * code.
10 :     *
11 :     *)
12 :     signature CELLS = sig
13 :     type register = int
14 :     type regmap = register Intmap.intmap
15 :     eqtype cellclass
16 :     exception Cells
17 :     val GP : cellclass (* general purpose register *)
18 :     val FP : cellclass (* floating point register *)
19 :     val CC : cellclass (* conditional code register *)
20 :     val MEM : cellclass (* memory *)
21 :     val CTRL : cellclass (* control dependence *)
22 :    
23 :     val stackptrR : int (* stack pointer register *)
24 :     val asmTmpR : int (* assembly temporary *)
25 :     val fasmTmp : int (* floating point temporary *)
26 :    
27 :     val newCell : cellclass -> unit -> register (* generate a new name *)
28 :     val numCell : cellclass -> unit -> int (* number of names in class *)
29 :     val maxCell : unit -> int (* max id of name *)
30 :     val cellToString : register * cellclass -> string
31 :    
32 :     val newReg : unit -> register (* newClass GP *)
33 :     val newFreg : unit -> register (* newClass FP *)
34 :     val newCCreg : unit -> register (* newClass CC *)
35 :    
36 :     val firstPseudo : register
37 :     val zero : cellclass -> register option
38 :     (* name of the register that contains zero *)
39 :    
40 :     val resetRegs : unit -> regmap (* reset any local state *)
41 :    
42 :     type cellset
43 :     val cellset2string : cellset -> string
44 :     val empty : cellset
45 :     val addCell : cellclass -> register * cellset -> cellset
46 :     val cellsetToRegs : regmap * cellset -> register list
47 :    
48 :     val addReg : register * cellset -> cellset (* addCell GP *)
49 :     val addFreg : register * cellset -> cellset (* addCell FP *)
50 :     end
51 :    
52 :    
53 :     (*
54 :     * $Log: cells.sig,v $
55 :     * Revision 1.4 1998/10/06 14:07:45 george
56 :     * Flowgraph has been removed from modules that do not need it.
57 :     * Changes to compiler/CodeGen/*/*{MLTree,CG}.sml necessary.
58 :     * [leunga]
59 :     *
60 :     * Revision 1.3 1998/05/25 15:11:02 george
61 :     * Fixed RCS keywords
62 :     *
63 :     *)

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0