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[smlnj] Diff of /sml/branches/SMLNJ/src/MLRISC/mlrisc/cells.sig
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Diff of /sml/branches/SMLNJ/src/MLRISC/mlrisc/cells.sig

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revision 105, Thu May 28 21:30:17 1998 UTC revision 106, Thu May 28 21:30:17 1998 UTC
# Line 11  Line 11 
11   *)   *)
12  signature CELLS = sig  signature CELLS = sig
13    
14      type regmap = int Intmap.intmap
15      eqtype cellclass
16      exception Cells
17      val GP   : cellclass  (* general purpose register *)
18      val FP   : cellclass  (* floating point register *)
19      val CC   : cellclass  (* conditional code register *)
20      val MEM  : cellclass  (* memory *)
21      val CTRL : cellclass  (* control dependence *)
22    
23    val stackptrR : int                   (* stack pointer register *)    val stackptrR : int                   (* stack pointer register *)
24    val asmTmpR : int                     (* assembly temporary *)    val asmTmpR : int                     (* assembly temporary *)
25    val fasmTmp : int                     (* floating point temporary *)    val fasmTmp : int                     (* floating point temporary *)
26    
27    val newReg    : unit -> int    val newCell : cellclass -> unit -> int (* generate a new name *)
28    val newFreg   : unit -> int    val numCell : cellclass -> unit -> int (* number of names in class *)
29    val newCCreg  : unit -> int    val maxCell : unit -> int              (* max id of name *)
30    val maxReg    : unit -> int    val cellToString : int * cellclass -> string
31    val maxFreg   : unit -> int  
32    val numRegs   : unit -> int    val newReg : unit -> int              (* newClass GP *)
33    val numFregs  : unit -> int    val newFreg : unit -> int             (* newClass FP *)
34      val newCCreg : unit -> int            (* newClass CC *)
35    val firstPseudoReg  : int  
36      val firstPseudo : int
37      val zero : cellclass -> int option
38           (* name of the register that contains zero *)
39    
40    val resetRegs : unit -> int Intmap.intmap    val resetRegs : unit -> regmap (* reset any local state *)
      (* reset any local state *)  
41    
42    type cellset    type cellset
43    val cellset2string : cellset -> string    val cellset2string : cellset -> string
   val addReg         : int * cellset -> cellset  
   val addFreg        : int * cellset -> cellset  
   val addCCreg       : int * cellset -> cellset  
44    val empty          : cellset    val empty          : cellset
45    val cellsetToRegs  : int Intmap.intmap * cellset -> int list    val addCell        : cellclass -> int * cellset -> cellset
46      val cellsetToRegs  : regmap * cellset -> int list
47    
48      val addReg  : int * cellset -> cellset (* addCell GP *)
49      val addFreg : int * cellset -> cellset (* addCell FP *)
50  end  end
51    
52    
53  (*  (*
54   * $Log: cells.sig,v $   * $Log: cells.sig,v $
55     * Revision 1.2  1998/05/19 15:47:05  george
56     *   The cells interface now makes registers an abstract type called cellclass.
57     *
58   * Revision 1.1.1.1  1998/04/08 18:39:02  george   * Revision 1.1.1.1  1998/04/08 18:39:02  george
59   * Version 110.5   * Version 110.5
60   *   *

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