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[smlnj] Diff of /sml/branches/SMLNJ/src/compiler/CodeGen/ppc/ppcCG.sml
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Diff of /sml/branches/SMLNJ/src/compiler/CodeGen/ppc/ppcCG.sml

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revision 247, Sat Apr 17 18:47:13 1999 UTC revision 411, Fri Sep 3 00:25:03 1999 UTC
# Line 1  Line 1 
1  functor PPCCG  functor PPCCG
2    (structure Emitter : EMITTER_NEW    (structure Emitter : INSTRUCTION_EMITTER
3       where I = PPCInstr and P = PPCPseudoOps) : MACHINE_GEN =       where I = PPCInstr
4           and P = PPCPseudoOps
5           and S.B = PPCMLTree.BNames) : MACHINE_GEN =
6  struct  struct
7    structure I = PPCInstr    structure I = PPCInstr
8    structure C = PPCCells    structure C = PPCCells
# Line 18  Line 20 
20    structure PPCRewrite = PPCRewrite(PPCInstr)    structure PPCRewrite = PPCRewrite(PPCInstr)
21    
22    (* properties of instruction set *)    (* properties of instruction set *)
23    structure P =    structure P = PPCProps(PPCInstr)
24      PPCProps(structure PPCInstr= I  
25                   structure Shuffle=PPCShuffle)    structure FreqProps = FreqProps(P)
26    
27    (* Label backpatching and basic block scheduling *)    (* Label backpatching and basic block scheduling *)
28    structure BBSched =    structure BBSched =
# Line 31  Line 33 
33               structure Emitter = Emitter)               structure Emitter = Emitter)
34    
35    (* flow graph pretty printing routine *)    (* flow graph pretty printing routine *)
36      (*
37    structure PrintFlowGraph =    structure PrintFlowGraph =
38       PrintFlowGraphFn (structure FlowGraph = F       PrintFlowGraphFn (structure FlowGraph = F
39                         structure Emitter   = Asm)                         structure Emitter   = Asm)
40       *)
41    
42    val intSpillCnt = Ctrl.getInt "ra-int-spills"    val intSpillCnt = Ctrl.getInt "ra-int-spills"
43    val floatSpillCnt = Ctrl.getInt "ra-float-spills"    val floatSpillCnt = Ctrl.getInt "ra-float-spills"
# Line 85  Line 89 
89      fun spill {regmap,instr,reg,id:B.name} = let      fun spill {regmap,instr,reg,id:B.name} = let
90        val offset = I.ImmedOp (getRegLoc(reg))        val offset = I.ImmedOp (getRegLoc(reg))
91        fun spillInstr(src) =        fun spillInstr(src) =
92          [I.ST{sz=I.Word, rs=src, ra=C.stackptrR, d=offset, mem=stack}]          [I.ST{st=I.STW, rs=src, ra=C.stackptrR, d=offset, mem=stack}]
93      in      in
94        intSpillCnt := !intSpillCnt + 1;        intSpillCnt := !intSpillCnt + 1;
95        case instr        case instr
# Line 111  Line 115 
115      fun fspill {regmap,instr,reg,id:B.name} = let      fun fspill {regmap,instr,reg,id:B.name} = let
116        val offset = I.ImmedOp (getFregLoc(reg))        val offset = I.ImmedOp (getFregLoc(reg))
117        fun spillInstr(src) =        fun spillInstr(src) =
118          [I.ST{sz=I.Double, rs=src, ra=C.stackptrR, d=offset, mem=stack}]          [I.STF{st=I.STFD, fs=src, ra=C.stackptrR, d=offset, mem=stack}]
119      in      in
120        floatSpillCnt := !floatSpillCnt + 1;        floatSpillCnt := !floatSpillCnt + 1;
121        case instr        case instr
# Line 137  Line 141 
141      fun reload{regmap,instr,reg,id:B.name} = let      fun reload{regmap,instr,reg,id:B.name} = let
142        val offset = I.ImmedOp (getRegLoc(reg))        val offset = I.ImmedOp (getRegLoc(reg))
143        fun reloadInstr(dst, rest) =        fun reloadInstr(dst, rest) =
144          I.L{sz=I.Word, rt=dst, ra=C.stackptrR, d=offset, mem=stack}::rest          I.L{ld=I.LWZ, rt=dst, ra=C.stackptrR, d=offset, mem=stack}::rest
145      in      in
146        intReloadCnt := !intReloadCnt + 1;        intReloadCnt := !intReloadCnt + 1;
147        case instr        case instr
# Line 153  Line 157 
157      fun freload {regmap, instr, reg, id:B.name} = let      fun freload {regmap, instr, reg, id:B.name} = let
158        val offset = I.ImmedOp (getFregLoc(reg))        val offset = I.ImmedOp (getFregLoc(reg))
159        fun reloadInstr(dst, rest) =        fun reloadInstr(dst, rest) =
160          I.L{sz=I.Double, rt=dst, ra=C.stackptrR, d=offset, mem=stack}::rest          I.LF{ld=I.LFD, ft=dst, ra=C.stackptrR, d=offset, mem=stack}::rest
161      in      in
162        floatReloadCnt := !floatReloadCnt + 1;        floatReloadCnt := !floatReloadCnt + 1;
163        case instr        case instr
# Line 171  Line 175 
175         regSpills := Intmap.new(8, RegSpills);         regSpills := Intmap.new(8, RegSpills);
176         fregSpills := Intmap.new(8, FregSpills))         fregSpills := Intmap.new(8, FregSpills))
177    
178      structure GR = GetReg(val nRegs=32 val available=R.availR)      structure GR = GetReg(val nRegs=32 val available=R.availR val first=0)
179      structure FR = GetReg(val nRegs=32 val available=R.availF)      structure FR = GetReg(val nRegs=32 val available=R.availF val first=32)
180    
181      structure PPCRa =      structure PPCRa =
182         PPCRegAlloc(structure P = P         PPCRegAlloc(structure P = P
# Line 218  Line 222 
222      val fCopyProp = FloatRa.ra FloatRa.COPY_PROPAGATION []      val fCopyProp = FloatRa.ra FloatRa.COPY_PROPAGATION []
223    
224      fun ra cluster = let      fun ra cluster = let
225        val pg = PrintFlowGraph.printCluster TextIO.stdOut        (* val pg = PrintFlowGraph.printCluster TextIO.stdOut *)
226        fun intRa cluster = (GR.reset(); iRegAlloc cluster)        fun intRa cluster = (GR.reset(); iRegAlloc cluster)
227        fun floatRa cluster = (FR.reset(); fRegAlloc cluster)        fun floatRa cluster = (FR.reset(); fRegAlloc cluster)
228      in spillInit(); (floatRa o intRa) cluster      in spillInit(); (floatRa o intRa) cluster
# Line 230  Line 234 
234    
235   (* primitives for generation of DEC alpha instruction flowgraphs *)   (* primitives for generation of DEC alpha instruction flowgraphs *)
236    structure FlowGraphGen =    structure FlowGraphGen =
237       FlowGraphGen(structure Flowgraph = F       ClusterGen(structure Flowgraph = F
238                    structure InsnProps = P                    structure InsnProps = P
239                    structure MLTree = MLTree                    structure MLTree = MLTree
240                    structure Stream=PPCStream
241                    val optimize = optimizerHook                    val optimize = optimizerHook
242                    val output = BBSched.bbsched o RegAllocation.ra)                    val output = BBSched.bbsched o RegAllocation.ra)
243    
# Line 240  Line 245 
245    structure MLTreeGen =    structure MLTreeGen =
246       MLRiscGen(structure MachineSpec=PPCSpec       MLRiscGen(structure MachineSpec=PPCSpec
247                 structure MLTreeComp=                 structure MLTreeComp=
248                    PPC(structure Flowgen=FlowGraphGen                    PPC(structure Stream=PPCStream
249                        structure PPCInstr=PPCInstr                        structure PPCInstr=PPCInstr
250                        structure PPCMLTree=PPCMLTree                        structure PPCMLTree=PPCMLTree
251                        structure PseudoInstrs=                        structure PseudoInstrs=
252                          PPCPseudoInstr(structure Instr=PPCInstr)                          PPCPseudoInstr(structure Instr=PPCInstr)
253                        val rs6000flag=false)                        val bit64mode=false
254                          val multCost=ref 6 (* an estimate *))
255                   structure Flowgen=FlowGraphGen
256                 structure Cells=PPCCells                 structure Cells=PPCCells
257                 structure C=PPCCpsRegs                 structure C=PPCCpsRegs
258                 structure PseudoOp=PPCPseudoOps)                 structure PseudoOp=PPCPseudoOps)

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