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[smlnj] Diff of /sml/branches/primop-branch-3/NOTES/HISTORY
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Diff of /sml/branches/primop-branch-3/NOTES/HISTORY

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revision 1123, Thu Mar 7 19:13:25 2002 UTC revision 1124, Thu Mar 7 19:49:22 2002 UTC
# Line 14  Line 14 
14    
15  ----------------------------------------------------------------------  ----------------------------------------------------------------------
16  Name: Lal George  Name: Lal George
17    Date: 2002/03/07 14:44:24 EST 2002
18    Tag: george-20020307-weighted-block-placement
19    
20    Tested the weighted block placement optimization on all architectures
21    (except the hppa) using AMPL to generate the block and edge frequencies.
22    Changes were required in the machine properties to correctly
23    categorize trap instructions. There is an MLRISC flag
24    "weighted-block-placement" that can be used to enable weighted block
25    placement, but this will be ineffective without block/edge
26    frequencies (coming soon).
27    
28    
29    ----------------------------------------------------------------------
30    Name: Lal George
31  Date: 2002/03/05 17:24:48 EST  Date: 2002/03/05 17:24:48 EST
32  Tag: george-20020305-linkage-cluster  Tag: george-20020305-linkage-cluster
33    
34  In order to support the block placement optimization, the first  In order to support the block placement optimization, a new cluster
35  cluster that is generated (called the linkage cluster) contains a jump  is generated as the very first cluster (called the linkage cluster).
36  to the entry point for the compilation unit. The linkage cluster  It contains a single jump to the 'real' entry point for the compilation
37  contains only one function, so block placement will have no effect on  unit. Block placement has no effect on the linkage cluster itself, but
38  the linkage cluster itself, but all the other clusters have full  all the other clusters  have full freedom in the manner in which they
39  freedom in the manner in which they reorder blocks or functions.  reorder blocks or functions.
40    
41  On the x86 the typical linkage code that is generated is:  On the x86 the typical linkage code that is generated is:
42     ----------------------     ----------------------
43          .align 2          .align 2
44     L0:     L0:
45          addl    $L1-L0, 72(%esp)          addl    $L1-L0, 72(%esp)
46          jmp     L0          jmp     L1
47    
48    
49          .align  2          .align  2
# Line 38  Line 52 
52    
53  72(%esp) is the memory location for the stdlink register. This  72(%esp) is the memory location for the stdlink register. This
54  must contain the address of the CPS function being called. In the  must contain the address of the CPS function being called. In the
55  above example, it contains the address of memory for  L0; before  above example, it contains the address of  L0; before
56  calling L1 (the real entry point for the compilation unit), it  calling L1 (the real entry point for the compilation unit), it
57  must contain the address for L1, and hence  must contain the address for L1, and hence
58    
59          addl $L1-L0, 72(%esp)          addl $L1-L0, 72(%esp)
60    
61  I have tested this on all architectures except the hppa.  I have tested this on all architectures except the hppa.The increase
62    in code size is of course negligible
63    
64  ----------------------------------------------------------------------  ----------------------------------------------------------------------
65  Name: Allen Leung  Name: Allen Leung

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