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[smlnj] Diff of /sml/trunk/HISTORY
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Diff of /sml/trunk/HISTORY

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revision 993, Fri Nov 23 02:37:10 2001 UTC revision 1009, Wed Jan 9 19:44:22 2002 UTC
# Line 8  Line 8 
8  The form of an entry should be:  The form of an entry should be:
9    
10  Name:  Name:
11  Date:  Date: yyyy/mm/dd
12  Tag: <post-commit CVS tag>  Tag: <post-commit CVS tag>
13  Description:  Description:
14    ----------------------------------------------------------------------
15    Name: Lal George
16    Date: 2001/01/09 14:31:35 EST 2002
17    Tag: george-20011206-rm-native-copy
18    Description:
19    
20            Removed the native COPY and FCOPY instructions
21            from all the architectures and replaced it with the
22            explicit COPY instruction from the previous commit.
23    
24            It is now possible to simplify many of the optimizations
25            modules that manipulate copies. This has not been
26            done in this change.
27    
28    ----------------------------------------------------------------------
29    Name: Lal George
30    Date: 2001/12/06 16:50:13 EST 2001
31    Tag: george-20011206-mlrisc-instruction
32    Description:
33    
34    Changed the representation of instructions from being fully abstract
35    to being partially concrete. That is to say:
36    
37      from
38            type instruction
39    
40      to
41            type instr                              (* machine instruction *)
42    
43            datatype instruction =
44                LIVE of {regs: C.cellset, spilled: C.cellset}
45              | KILL of {regs: C.cellset, spilled: C.cellset}
46              | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
47              | ANNOTATION of {i: instruction, a: Annotations.annotation}
48              | INSTR of instr
49    
50    This makes the handling of certain special instructions that appear on
51    all architectures easier and uniform.
52    
53    LIVE and KILL say that a list of registers are live or killed at the
54    program point where they appear. No spill code is generated when an
55    element of the 'regs' field is spilled, but the register is moved to
56    the 'spilled' (which is present, more for debugging than anything else).
57    
58    LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
59    We used to generate:
60    
61            DEFFREG f1
62            f1 := f2 + f3
63            trapb
64    
65    but now generate:
66    
67            f1 := f2 + f3
68            trapb
69            LIVE {regs=[f1,f2,f3], spilled=[]}
70    
71    Furthermore, the DEFFREG (hack) required that all floating point instruction
72    use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
73    defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
74    in a cleaner alpha implementation. (Hopefully, intel will not get rid of
75    this architecture).
76    
77    COPYXXX is intended to replace the parallel COPY and FCOPY  available on
78    all the architectures. This will result in further simplification of the
79    register allocator that must be aware of them for coalescing purposes, and
80    will also simplify certain aspects of the machine description that provides
81    callbacks related to parallel copies.
82    
83    ANNOTATION should be obvious, and now INSTR represents the honest to God
84    machine instruction set!
85    
86    The <arch>/instructions/<arch>Instr.sml files define certain utility
87    functions for making porting easier -- essentially converting upper case
88    to lower case. All machine instructions (of type instr) are in upper case,
89    and the lower case form generates an MLRISC instruction. For example on
90    the alpha we have:
91    
92      datatype instr =
93         LDA of {r:cell, b:cell, d:operand}
94       | ...
95    
96      val lda : {r:cell, b:cell, d:operand} -> instruction
97        ...
98    
99    where lda is just (INSTR o LDA), etc.
100    
101  ----------------------------------------------------------------------  ----------------------------------------------------------------------
102  Name: Matthias Blume  Name: Matthias Blume

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