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Diff of /sml/trunk/HISTORY

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revision 1002, Fri Nov 30 17:11:33 2001 UTC revision 1003, Fri Dec 7 02:45:32 2001 UTC
# Line 8  Line 8 
8  The form of an entry should be:  The form of an entry should be:
9    
10  Name:  Name:
11  Date:  Date: yyyy/mm/dd
12  Tag: <post-commit CVS tag>  Tag: <post-commit CVS tag>
13  Description:  Description:
14    ----------------------------------------------------------------------
15    Name: Lal George
16    Date: 2001/12/06 16:50:13 EST 2001
17    Tag: george-20011206-mlrisc-instruction
18    Description:
19    
20    Changed the representation of instructions from being fully abstract
21    to being partially concrete. That is to say:
22    
23      from
24            type instruction
25    
26      to
27            type instr                              (* machine instruction *)
28    
29            datatype instruction =
30                LIVE of {regs: C.cellset, spilled: C.cellset}
31              | KILL of {regs: C.cellset, spilled: C.cellset}
32              | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
33              | ANNOTATION of {i: instruction, a: Annotations.annotation}
34              | INSTR of instr
35    
36    This makes the handling of certain special instructions that appear on
37    all architectures easier and uniform.
38    
39    LIVE and KILL say that a list of registers are live or killed at the
40    program point where they appear. No spill code is generated when an
41    element of the 'regs' field is spilled, but the register is moved to
42    the 'spilled' (which is present, more for debugging than anything else).
43    
44    LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
45    We used to generate:
46    
47            DEFFREG f1
48            f1 := f2 + f3
49            trapb
50    
51    but now generate:
52    
53            f1 := f2 + f3
54            trapb
55            LIVE {regs=[f1,f2,f3], spilled=[]}
56    
57    Furthermore, the DEFFREG (hack) required that all floating point instruction
58    use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
59    defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
60    in a cleaner alpha implementation. (Hopefully, intel will not get rid of
61    this architecture).
62    
63    COPYXXX is intended to replace the parallel COPY and FCOPY  available on
64    all the architectures. This will result in further simplification of the
65    register allocator that must be aware of them for coalescing purposes, and
66    will also simplify certain aspects of the machine description that provides
67    callbacks related to parallel copies.
68    
69    ANNOTATION should be obvious, and now INSTR represents the honest to God
70    machine instruction set!
71    
72    The <arch>/instructions/<arch>Instr.sml files define certain utility
73    functions for making porting easier -- essentially converting upper case
74    to lower case. All machine instructions (of type instr) are in upper case,
75    and the lower case form generates an MLRISC instruction. For example on
76    the alpha we have:
77    
78      datatype instr =
79         LDA of {r:cell, b:cell, d:operand}
80       | ...
81    
82      val lda : {r:cell, b:cell, d:operand} -> instruction
83        ...
84    
85    where lda is just (INSTR o LDA), etc.
86    
87  ----------------------------------------------------------------------  ----------------------------------------------------------------------
88  Name: Matthias Blume  Name: Matthias Blume

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