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Revision 430 - (download) (annotate)
Wed Sep 8 09:47:00 1999 UTC (19 years, 10 months ago) by monnier
File size: 9963 byte(s)
This commit was generated by cvs2svn to compensate for changes in r429,
which included commits to RCS files with non-trunk default branches.
Changes to the MLRISC system
============================

110.20
======
1.  Changed the interface to MLTREECOMP.  It now uses the STREAM interface.
2.  Library code has been streamlined.  Lot's of things are now replaced
    by stuff in comp-lib and smlnj-lib.
3.  Dominator tree code has been improved.  It is now possible to
    compute the dominator tree without also computing the postdominator
    tree (and vice versa).  What was I thinking?
4.  Some changes to the RA that takes advantage of the new Intmap functions.
5.  CFGGen and friends have been fixed.  CFGGen is the functor that
    builds the CFG directly.  It now works!  I recompiled the
    compiler with it.  But it is a few percentages slower because 
    we have to go thru the CFG -> cluster phase.
6.  Labels have been improved/simplified.
7.  Some additions to handle CVTI2I in MLTREE.  Not yet tested.
8.  Various fixes to x86PseudoR to handle annotation propagation and
    non identity regmaps.
9.  Factored the MLRISC sources into separate libraries.
10. A very subtle bug involving the entry labels has been fixed.
    How did things work before?

110.19
======

1.  MLTREE
    ------
    As per Lal's suggestions, the MLTREE language has be extended so that
    all operators are now explicitly typed (by the data width).   This 
    change involves drastically extending the instruction sets of all the
    supported architectures to support 16/64 bit operations and single
    precision floating points.   
 
    STATUS: There are still a few rough spots but should be relatively
    stable, at least for SML/NJ use. In any case the new system is 
    running under the SPARC, HPPA and x86 platforms for a while now.  

    Lal is currently looking at the LI/LI32/LI64 business.  These
    may be replaced by LI of IntInf.int soon.

2.  MDGEN
    -----

    Some of the new machine description modules, noteably the cells 
    modules, machine code emitter and the assemblers are generated by 
    a new machine description tool MDGEN.  

    STATUS: The tool is quite rough right now.  I consider this a 
    proof of concept.  Eventually I want to make all it possible to 
    generate all the modules.   

    NOTE: Most of the ideas in the tool are stolen from/inspired by 
    Norman Ramsey's Lambda RTL and his NJ Machine Code Toolkit.  
    However, I think my way to describing machine encoding is much more
    natural than his scheme.

    GOOD SPOT:  The alpha machine description is the cleanest.

    MISSING FEATURES: There should be extensions to deal with bit field
    manipulations.  The HPPA machine description is particularly ugly (lot's
    of procedural code) because of this lack.  

3.  Cells
    -----

    The cells interface has been vastly expanded.  Also, the encoding
    of physical registers has been changed: all physical register
    are now encoded uniquely.  For example, on the Sparc, %g0 is encoding
    as 0 and %f0 is encoding as 32.  The client should use the
    function Reg provided by the cells interface to compute these new encoding.
 
         val Reg : cellkind -> int -> register

    For example, to describe %f0, use 

        SparcCells.Reg SparcCells.FP 0

    STATUS: Quite solid I think.

4.  RA
    --

    The RA has been reorganized a bit; the new RA is functionally identical 
    to the old one but I think it is slightly faster than before.  Some
    of the internal data structures have been changed.

    STATUS: The GetReg interface has been changed.  The change is needed
    to support the new Cells encoding, and for improved efficiency.

4a  Newest RA
    ---------
 
    There is a completely new RA that I'm building which incorporates a lot
    of extensions: register pair coloring, priority base coalesce/freeze,
    priority based spilling, support for splitting and rematerialization,
    plus support for machine SSA.

    STATUS: Not all features are there yet.  Don't use it.

5.  Instruction Selection Modules
    -----------------------------

    The instruction selection modules have been changed to support the
    new MLTREE language.

6.  MLTREE as RTL
    -------------

    The SSA optimizations need a way of specifying semantics of instructions.
    In the old system it was some combinator-like language I hacked up.
    It worked but not entirely satisfactory.  In the new system the MLTREE
    language doubles as this purpose.  

    STATUS: Getting there soon.

7.  MLTREE as High Level IR
    -----------------------

    There is now a way of using the MLTREE language as if it were
    a ``high level'' instruction set.  Theoretically, it means that 
    all the optimizations I've developed for the low level instruction sets 
    can be directly applied to MLTREE.  

    STATUS: Missing some machine descriptions.  Untested.

8.  MLRISC IR
    ---------
   
    MLRISC IR is the IR that I use for all optimizations.  It includes
    stuff like (post-)dominator tree, control dependence graph, interval
    structure, static branch predication, liveness analysis, visualization etc. 

    There is now a way to generate MLRISC IR directly from MLTREE, bypassing
    the cluster representation.  Of course, the cluster and the MLRISC IR
    are still inter-convertible.

    STATUS: Pretty solid nowadays.  Need some users/beta-testers.

9.  SSA
    ---

    I'm in the process of porting/improving the SSA stuff.  Lots of 
    changes here.  

    STATUS: Not ready for primetime yet.  Mainly because moving to a new
    RTL, plus having to support the new instructions broke a lot of stuff. 

10. EPIC/VLIW support
    -----------------

    I've incorporating all the stuff I've done for Nevin last summer
    in this release.  They are quite solid I think.

    NOTE: We need machine descriptions!  

11. Hyperblock scheduling/modulo scheduling
    ---------------------------------------

    STATUS: Same as above. 

12. Superscalar scheduling
    ----------------------

    STATUS: I'm rewriting these from scratch right now.  Kind of
    slow in progress since other things have the priority.

    NOTE: There used to be a tool that generates automata describing the 
    reservation table state during scheduling.  This is written in Perl.
    It should be ported to SML. 

13. GC Safety
    ---------

    STATUS: Vapor for now.

14. Annotations
    -----------

    Annotations can now be propagated to the instructions.   
    I'm using it to propagate branch probabilities in the SML/NJ compiler:
    GC tests are assigned branch probabilities of zero, so that all
    optimizations that are frequency driven can take the correct action.

    STATUS: quite solid I think.

15. Regions (Memory aliasing annotations)
    -------------------------------------

    There is a new way to describing regions in the new MLRiscRegions 
    interface.  This is the stuff that Fermin and I have been talking about.

    STATUS: Nobody is using it yet.

16. Control Dependence
    ------------------

    There should be a way of specifying control dependence (and anti-dependence)
    in MLTREE.  This lack is currently a major sore point for me since
    I have to play tricks in my optimizations (moving loads and stores
    correctly require these information.)  This should be tied into
    the Regions business.

    STATUS: Urgently needed but should be simple to implement.

17. Instruction Stream
    ------------------

    There is now a new concept of ``instruction stream'' in MLRISC.
    It is mainly used to standarized a few common interfaces used
    in the assemblers, machine code emitters, and the instruction 
    selection modules.   The main advantage of the stream interface 
    is that it encapsulates all the state so that it is possible to
    have multiple instances of the thing going.

    STATUS: very solid.

18. Optimizations in the Instruction Selection Modules
    --------------------------------------------------

    During the rewrite of the instruction selection modules, I've added
    a few optimizations.  These include support for more addressing modes 
    (HPPA), support for scale-and-add instructions (HPPA, Alpha), and
    support for strength reduction of multiplication and division (all).

    To support the last bit, there is now a generic module for generating 
    better multiplication and division code.  It is specialized
    to the particular architecture at hand.

    STATUS: The algorithm used in this module should be improved. 
    Specifically, a dynamic programming algorithm should be used for
    searching for good multiplication instruction sequences.  The algorithm
    in the recent paper in PLDI should be used to generate instructions 
    for division by a constant.  Also, no 64-bit support is yet in.  
 
19. Delay Slot Filling
    ------------------

    The module SpanDependencyResolution has been around for a few releases
    now (since the sparc backend).  It performs delay slot filling while
    emitting machine code.

    In addition, a new module for delay slot filling for assembly 
    output is added.  This should be useful for all backends that do not 
    directly emit machine code.  For example C--.

    STATUS: Untested.

20. Cluster
    -------

    Frequencies annotations are added.  This is part of my evil plan to
    convert everything in MLRISC to be driven by frequencies.

    Also there is a now a module to gives clusters a graph view, and 
    a module for visualizing a cluster.  These should be useful for
    those who don't want to use the MLRISC IR stuff but still want to
    take advantage of the visualization stuff.

    NOTE: Annotations on the block and edge level should be also added, 
    as in the MLRISC IR representation.

21. Documentation
    -------------

    The directory Doc is supposed to contain all the documentation
    for the new stuff.  But....

    STATUS: Not ready for primetime.

Allen Leung (leunga@cs.nyu.edu)
June 6th, 1999

root@smlnj-gforge.cs.uchicago.edu
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