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View of /sml/trunk/src/MLRISC/Doc/latex/VLIW.tex

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Revision 651 - (download) (as text) (annotate)
Thu Jun 1 18:34:03 2000 UTC (19 years, 2 months ago) by monnier
File size: 671 byte(s)
bring revisions from the vendor branch to the trunk
\section{Optimizations for VLIW/EPIC Architectures}

Many newer architectures such as the upcoming IA-64 and the
DSPs such as the C6 are VLIW or so called EPIC machines.  
These architectures depends on the compiler to 
extract instruction level parallelism (\newdef{ILP})
and data level parallelism (\newdef{DLP}).

Optimizations for these architectures include:
  \item Hyperblock construction
  \item Predication and predicate analysis
  \item Hyperblock scheduling
  \item Modulo scheduling

\subsection{Predicate Analysis}
\subsection{Hyperblock Scheduling}
\subsection{Modulo Scheduling}

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