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[smlnj] Annotation of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml
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Annotation of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml

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1 : monnier 409 (*
2 :     * This is a revamping of the Alpha32 instruction selection module
3 :     * using the new MLTREE and instruction representation. I've dropped
4 :     * the suffix 32 since we now support 64 bit datatypes.
5 :     *
6 :     * -- Allen
7 :     *
8 :     * Notes: places with optimizations are marked ***OPT***
9 :     *)
10 :    
11 :     functor Alpha
12 : leunga 744 (structure AlphaInstr : ALPHAINSTR
13 : monnier 409 structure AlphaMLTree : MLTREE
14 :     structure PseudoInstrs : ALPHA_PSEUDO_INSTR
15 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
16 :     where T = AlphaMLTree and I = AlphaInstr
17 : monnier 475 sharing AlphaMLTree.Region = AlphaInstr.Region
18 : george 545 sharing AlphaMLTree.LabelExp = AlphaInstr.LabelExp
19 : monnier 475 sharing PseudoInstrs.I = AlphaInstr
20 :     sharing PseudoInstrs.T = AlphaMLTree
21 : monnier 409
22 :     (* Cost of multiplication in cycles *)
23 :     val multCost : int ref
24 :    
25 :     (* Should we just use the native multiply by a constant? *)
26 :     val useMultByConst : bool ref
27 : george 545
28 :     (* Should we use SUD flags for floating point and generate DEFFREG?
29 :     * This should be set to false for C-like clients but true for SML/NJ.
30 :     *)
31 :     val SMLNJfloatingPoint : bool
32 : leunga 583
33 :     (* Should we use generate special byte/word load instructions
34 :     * like LDBU, LDWU, STB, STW.
35 :     *)
36 :     val byteWordLoadStores : bool ref
37 : monnier 409 ) : MLTREECOMP =
38 :     struct
39 :    
40 :     structure T = AlphaMLTree
41 : monnier 429 structure S = T.Stream
42 : monnier 409 structure R = AlphaMLTree.Region
43 :     structure I = AlphaInstr
44 :     structure C = AlphaInstr.C
45 : george 545 structure LE = I.LabelExp
46 : monnier 409 structure W32 = Word32
47 : monnier 429 structure P = PseudoInstrs
48 : george 545 structure A = MLRiscAnnotations
49 : monnier 409
50 :     (*********************************************************
51 :    
52 :     Trap Shadows, Floating Exceptions, and Denormalized
53 :     Numbers on the DEC Alpha
54 :    
55 :     Andrew W. Appel and Lal George
56 :     Nov 28, 1995
57 :    
58 :     See section 4.7.5.1 of the Alpha Architecture Reference Manual.
59 :    
60 :     The Alpha has imprecise exceptions, meaning that if a floating
61 :     point instruction raises an IEEE exception, the exception may
62 :     not interrupt the processor until several successive instructions have
63 :     completed. ML, on the other hand, may want a "precise" model
64 :     of floating point exceptions.
65 :    
66 :     Furthermore, the Alpha hardware does not support denormalized numbers
67 :     (for "gradual underflow"). Instead, underflow always rounds to zero.
68 :     However, each floating operation (add, mult, etc.) has a trapping
69 :     variant that will raise an exception (imprecisely, of course) on
70 :     underflow; in that case, the instruction will produce a zero result
71 :     AND an exception will occur. In fact, there are several variants
72 :     of each instruction; three variants of MULT are:
73 :    
74 :     MULT s1,s2,d truncate denormalized result to zero; no exception
75 :     MULT/U s1,s2,d truncate denormalized result to zero; raise UNDERFLOW
76 :     MULT/SU s1,s2,d software completion, producing denormalized result
77 :    
78 :     The hardware treats the MULT/U and MULT/SU instructions identically,
79 :     truncating a denormalized result to zero and raising the UNDERFLOW
80 :     exception. But the operating system, on an UNDERFLOW exception,
81 :     examines the faulting instruction to see if it's an /SU form, and if so,
82 :     recalculates s1*s2, puts the right answer in d, and continues,
83 :     all without invoking the user's signal handler.
84 :    
85 :     Because most machines compute with denormalized numbers in hardware,
86 :     to maximize portability of SML programs, we use the MULT/SU form.
87 :     (and ADD/SU, SUB/SU, etc.) But to use this form successfully,
88 :     certain rules have to be followed. Basically, d cannot be the same
89 :     register as s1 or s2, because the opsys needs to be able to
90 :     recalculate the operation using the original contents of s1 and s2,
91 :     and the MULT/SU instruction will overwrite d even if it traps.
92 :    
93 :     More generally, we may want to have a sequence of floating-point
94 :     instructions. The rules for such a sequence are:
95 :    
96 :     1. The sequence should end with a TRAPB (trap barrier) instruction.
97 :     (This could be relaxed somewhat, but certainly a TRAPB would
98 :     be a good idea sometime before the next branch instruction or
99 :     update of an ML reference variable, or any other ML side effect.)
100 :     2. No instruction in the sequence should destroy any operand of itself
101 :     or of any previous instruction in the sequence.
102 :     3. No two instructions in the sequence should write the same destination
103 :     register.
104 :    
105 :     We can achieve these conditions by the following trick in the
106 :     Alpha code generator. Each instruction in the sequence will write
107 :     to a different temporary; this is guaranteed by the translation from
108 :     ML-RISC. At the beginning of the sequence, we will put a special
109 :     pseudo-instruction (we call it DEFFREG) that "defines" the destination
110 :     register of the arithmetic instruction. If there are K arithmetic
111 :     instructions in the sequence, then we'll insert K DEFFREG instructions
112 :     all at the beginning of the sequence.
113 :     Then, each arithop will not only "define" its destination temporary
114 :     but will "use" it as well. When all these instructions are fed to
115 :     the liveness analyzer, the resulting interference graph will then
116 :     have inteference edges satisfying conditions 2 and 3 above.
117 :    
118 :     Of course, DEFFREG doesn't actually generate any code. In our model
119 :     of the Alpha, every instruction generates exactly 4 bytes of code
120 :     except the "span-dependent" ones. Therefore, we'll specify DEFFREG
121 :     as a span-dependent instruction whose minimum and maximum sizes are zero.
122 :    
123 :     At the moment, we do not group arithmetic operations into sequences;
124 :     that is, each arithop will be preceded by a single DEFFREG and
125 :     followed by a TRAPB. To avoid the cost of all those TRAPB's, we
126 :     should improve this when we have time. Warning: Don't put more
127 :     than 31 instructions in the sequence, because they're all required
128 :     to write to different destination registers!
129 :    
130 :     What about multiple traps? For example, suppose a sequence of
131 :     instructions produces an Overflow and a Divide-by-Zero exception?
132 :     ML would like to know only about the earliest trap, but the hardware
133 :     will report BOTH traps to the operating system. However, as long
134 :     as the rules above are followed (and the software-completion versions
135 :     of the arithmetic instructions are used), the operating system will
136 :     have enough information to know which instruction produced the
137 :     trap. It is very probable that the operating system will report ONLY
138 :     the earlier trap to the user process, but I'm not sure.
139 :    
140 :     For a hint about what the operating system is doing in its own
141 :     trap-handler (with software completion), see section 6.3.2 of
142 :     "OpenVMS Alpha Software" (Part II of the Alpha Architecture
143 :     Manual). This stuff should apply to Unix (OSF1) as well as VMS.
144 :    
145 :     ****************************************************************)
146 :    
147 :     fun error msg = MLRiscErrorMsg.error("Alpha",msg)
148 :    
149 : leunga 744 type instrStream = (I.instruction,C.cellset) T.stream
150 :     type mltreeStream = (T.stm,T.mlrisc list) T.stream
151 : monnier 409
152 :     (*
153 :     * This module is used to simulate operations of non-standard widths.
154 :     *)
155 :     structure Gen = MLTreeGen(structure T = T
156 :     val intTy = 64
157 :     val naturalWidths = [32,64]
158 : monnier 429 datatype rep = SE | ZE | NEITHER
159 :     val rep = SE
160 : monnier 409 )
161 :    
162 : leunga 744 val zeroR = C.r31
163 : monnier 409 val zeroOpn = I.REGop zeroR
164 : george 761 fun LI i = T.LI(T.I.fromInt(32, i))
165 :     fun toInt i = T.I.toInt(32, i)
166 :     val int_0 = T.I.int_0
167 :     val int_1 = T.I.int_1
168 :     fun EQ(x,y) = T.I.EQ(32, x, y)
169 :     fun GE(x,y) = T.I.GE(32, x, y)
170 :     fun LE(x,y) = T.I.LE(32, x, y)
171 :     fun LT(x,y) = T.I.LT(32, x, y)
172 : monnier 409
173 :     (*
174 :     * Specialize the modules for multiplication/division
175 :     * by constant optimizations.
176 :     *)
177 :     functor Multiply32 = MLTreeMult
178 :     (structure I = I
179 :     structure T = T
180 :    
181 :     val intTy = 32
182 :    
183 : monnier 429 type arg = {r1:C.cell,r2:C.cell,d:C.cell}
184 :     type argi = {r:C.cell,i:int,d:C.cell}
185 : monnier 409
186 :     fun mov{r,d} = I.COPY{dst=[d],src=[r],tmp=NONE,impl=ref NONE}
187 :     fun add{r1,r2,d} = I.OPERATE{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}
188 :     (*
189 :     * How to left shift by a constant (32bits)
190 :     *)
191 :     fun slli{r,i=1,d} = [I.OPERATE{oper=I.ADDL,ra=r,rb=I.REGop r,rc=d}]
192 :     | slli{r,i=2,d} = [I.OPERATE{oper=I.S4ADDL,ra=r,rb=zeroOpn,rc=d}]
193 :     | slli{r,i=3,d} = [I.OPERATE{oper=I.S8ADDL,ra=r,rb=zeroOpn,rc=d}]
194 :     | slli{r,i,d} =
195 :     let val tmp = C.newReg()
196 :     in [I.OPERATE{oper=I.SLL,ra=r,rb=I.IMMop i,rc=tmp},
197 : leunga 646 I.OPERATE{oper=I.ADDL,ra=tmp,rb=zeroOpn,rc=d}]
198 : monnier 409 end
199 :    
200 :     (*
201 :     * How to right shift (unsigned) by a constant (32bits)
202 :     *)
203 :     fun srli{r,i,d} =
204 :     let val tmp = C.newReg()
205 :     in [I.OPERATE{oper=I.ZAP,ra=r,rb=I.IMMop 0xf0,rc=tmp},
206 :     I.OPERATE{oper=I.SRL,ra=tmp,rb=I.IMMop i,rc=d}]
207 :     end
208 :    
209 :     (*
210 :     * How to right shift (signed) by a constant (32bits)
211 :     *)
212 :     fun srai{r,i,d} =
213 :     let val tmp = C.newReg()
214 : leunga 646 in [I.OPERATE{oper=I.ADDL,ra=r,rb=zeroOpn,rc=tmp},
215 : monnier 409 I.OPERATE{oper=I.SRA,ra=tmp,rb=I.IMMop i,rc=d}]
216 :     end
217 :     )
218 :    
219 :     functor Multiply64 = MLTreeMult
220 :     (structure I = I
221 :     structure T = T
222 :    
223 :     val intTy = 64
224 :    
225 : monnier 429 type arg = {r1:C.cell,r2:C.cell,d:C.cell}
226 :     type argi = {r:C.cell,i:int,d:C.cell}
227 : monnier 409
228 :     fun mov{r,d} = I.COPY{dst=[d],src=[r],tmp=NONE,impl=ref NONE}
229 :     fun add{r1,r2,d}= I.OPERATE{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}
230 :     fun slli{r,i,d} = [I.OPERATE{oper=I.SLL,ra=r,rb=I.IMMop i,rc=d}]
231 :     fun srli{r,i,d} = [I.OPERATE{oper=I.SRL,ra=r,rb=I.IMMop i,rc=d}]
232 :     fun srai{r,i,d} = [I.OPERATE{oper=I.SRA,ra=r,rb=I.IMMop i,rc=d}]
233 :     )
234 :    
235 :     (* signed, trapping version of multiply and divide *)
236 :     structure Mult32 = Multiply32
237 :     (val trapping = true
238 :     val multCost = multCost
239 :     fun addv{r1,r2,d} = [I.OPERATEV{oper=I.ADDLV,ra=r1,rb=I.REGop r2,rc=d}]
240 :     fun subv{r1,r2,d} = [I.OPERATEV{oper=I.SUBLV,ra=r1,rb=I.REGop r2,rc=d}]
241 :     val sh1addv = NONE
242 :     val sh2addv = NONE
243 :     val sh3addv = NONE
244 :     )
245 : monnier 429 (val signed = true)
246 : monnier 409
247 : monnier 429 (* non-trapping version of multiply and divide *)
248 :     functor Mul32 = Multiply32
249 : monnier 409 (val trapping = false
250 :     val multCost = multCost
251 :     fun addv{r1,r2,d} = [I.OPERATE{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}]
252 :     fun subv{r1,r2,d} = [I.OPERATE{oper=I.SUBL,ra=r1,rb=I.REGop r2,rc=d}]
253 :     val sh1addv = NONE
254 :     val sh2addv = SOME(fn {r1,r2,d} =>
255 :     [I.OPERATE{oper=I.S4ADDL,ra=r1,rb=I.REGop r2,rc=d}])
256 :     val sh3addv = SOME(fn {r1,r2,d} =>
257 :     [I.OPERATE{oper=I.S8ADDL,ra=r1,rb=I.REGop r2,rc=d}])
258 :     )
259 : monnier 429 structure Mulu32 = Mul32(val signed = false)
260 :     structure Muls32 = Mul32(val signed = true)
261 : monnier 409
262 :     (* signed, trapping version of multiply and divide *)
263 :     structure Mult64 = Multiply64
264 :     (val trapping = true
265 :     val multCost = multCost
266 :     fun addv{r1,r2,d} = [I.OPERATEV{oper=I.ADDQV,ra=r1,rb=I.REGop r2,rc=d}]
267 :     fun subv{r1,r2,d} = [I.OPERATEV{oper=I.SUBQV,ra=r1,rb=I.REGop r2,rc=d}]
268 :     val sh1addv = NONE
269 :     val sh2addv = NONE
270 :     val sh3addv = NONE
271 :     )
272 : monnier 429 (val signed = true)
273 : monnier 409
274 :     (* unsigned, non-trapping version of multiply and divide *)
275 : monnier 429 functor Mul64 = Multiply64
276 : monnier 409 (val trapping = false
277 :     val multCost = multCost
278 :     fun addv{r1,r2,d} = [I.OPERATE{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}]
279 :     fun subv{r1,r2,d} = [I.OPERATE{oper=I.SUBQ,ra=r1,rb=I.REGop r2,rc=d}]
280 :     val sh1addv = NONE
281 :     val sh2addv = SOME(fn {r1,r2,d} =>
282 :     [I.OPERATE{oper=I.S4ADDQ,ra=r1,rb=I.REGop r2,rc=d}])
283 :     val sh3addv = SOME(fn {r1,r2,d} =>
284 :     [I.OPERATE{oper=I.S8ADDQ,ra=r1,rb=I.REGop r2,rc=d}])
285 :     )
286 : monnier 429 structure Mulu64 = Mul64(val signed = false)
287 :     structure Muls64 = Mul64(val signed = true)
288 : monnier 409
289 :     (*
290 :     * The main stuff
291 :     *)
292 :    
293 : george 761 datatype times4or8 = TIMES1 | TIMES4 | TIMES8
294 : monnier 409 datatype zeroOne = ZERO | ONE | OTHER
295 :     datatype commutative = COMMUTE | NOCOMMUTE
296 :    
297 : leunga 744 val zeroFR = C.f31
298 : leunga 583 val zeroEA = I.Direct zeroR
299 : george 761 val zeroT = T.LI int_0
300 : leunga 583 val trapb = [I.TRAPB]
301 :     val zeroImm = I.IMMop 0
302 :    
303 : monnier 409 fun selectInstructions
304 : george 545 (instrStream as
305 :     S.STREAM{emit,beginCluster,endCluster,
306 : monnier 429 defineLabel,entryLabel,pseudoOp,annotation,
307 : leunga 744 exitBlock,comment,...}) =
308 : monnier 409 let
309 :     infix || && << >> ~>>
310 :    
311 :     val op || = W32.orb
312 :     val op && = W32.andb
313 :     val op << = W32.<<
314 :     val op >> = W32.>>
315 :     val op ~>> = W32.~>>
316 :    
317 :     val itow = Word.fromInt
318 :     val wtoi = Word.toIntX
319 :    
320 :     val newReg = C.newReg
321 :     val newFreg = C.newFreg
322 :    
323 :     (* Choose the appropriate rounding mode to generate.
324 :     * This stuff is used to support the alpha32x SML/NJ backend.
325 : monnier 429 *
326 :     *
327 :     * Floating point rounding mode.
328 :     * When this is set to true, we use the /SU rounding mode
329 :     * (chopped towards zero) for floating point arithmetic.
330 :     * This flag is only used to support the old alpha32x backend.
331 :     *
332 :     * Otherwise, we use /SUD. This is the default for SML/NJ.
333 :     *
334 : monnier 409 *)
335 : george 545 val (ADDTX,SUBTX,MULTX,DIVTX) =
336 :     (I.ADDTSUD,I.SUBTSUD,I.MULTSUD,I.DIVTSUD)
337 :     val (ADDSX,SUBSX,MULSX,DIVSX) =
338 :     (I.ADDSSUD,I.SUBSSUD,I.MULSSUD,I.DIVSSUD)
339 : monnier 409
340 :     fun mark'(i,[]) = i
341 :     | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
342 :     fun mark(i,an) = emit(mark'(i,an))
343 :    
344 :     (* Fit within 16 bits? *)
345 :     fun literal16 n = ~32768 <= n andalso n < 32768
346 :     fun literal16w w =
347 :     let val hi = W32.~>>(w,0wx16)
348 :     in hi = 0w0 orelse (W32.notb hi) = 0w0 end
349 :    
350 :     (* emit an LDA instruction; return the register that holds the value *)
351 :     fun lda(base,I.IMMop 0) = base
352 :     | lda(base,offset) =
353 :     let val r = newReg()
354 :     in emit(I.LDA{r=r, b=base, d=offset}); r end
355 :    
356 :     (* emit load immed *)
357 : george 761 fun loadImmed(n, base, rd, an) = let
358 :     val n = T.I.toInt32(32, n)
359 :     in
360 :     if n = 0 then move(base, rd, an)
361 :     else if ~32768 <= n andalso n < 32768 then
362 :     mark(I.LDA{r=rd, b=base, d=I.IMMop(Int32.toInt n)}, an)
363 :     else loadImmed32(n, base, rd, an)
364 : monnier 409 end
365 :    
366 :     (* loadImmed32 is used to load int32 and word32 constants.
367 :     * In either case we sign extend the 32-bit value. This is compatible
368 :     * with LDL which sign extends a 32-bit valued memory location.
369 :     *)
370 : george 761 (* TODO:
371 :     * Should handle 64 bits if immediate is not in the 32 bit range.
372 :     *)
373 :     and loadImmed32(n, base, rd, an) = let
374 :     fun immed(0, high) =
375 :     mark(I.LDAH{r=rd, b=base, d=I.IMMop(high)}, an)
376 :     | immed(low, 0) =
377 :     mark(I.LDA{r=rd, b=base, d=I.IMMop(low)}, an)
378 :     | immed(low, high) =
379 :     (emit(I.LDA{r=rd, b=base, d=I.IMMop(low)});
380 :     mark(I.LDAH{r=rd, b=rd, d=I.IMMop(high)}, an)
381 :     )
382 :     val w = Word32.fromLargeInt(Int32.toLarge n)
383 :     val low = W32.andb(w, 0wxffff)
384 :     val high = W32.~>>(w, 0w16)
385 :     in
386 :     if W32.<(low, 0wx8000) then
387 :     immed(W32.toInt low, W32.toIntX high)
388 :     else let
389 :     val low = W32.toIntX(W32.-(low, 0wx10000))
390 :     val high = W32.toIntX(W32.+(high, 0w1))
391 : monnier 409 in
392 : george 761 if high <> 0x8000 then immed(low, high)
393 :     else let (* transition of high from pos to neg *)
394 :     val tmpR1 = newReg()
395 :     val tmpR2 = newReg()
396 :     val tmpR3=newReg()
397 :     in
398 :     (* you just gotta do, what you gotta do! *)
399 :     emit(I.LDA{r=tmpR3, b=base, d=I.IMMop(low)});
400 :     emit(I.OPERATE{oper=I.ADDQ, ra=zeroR, rb=I.IMMop 1, rc=tmpR1});
401 :     emit(I.OPERATE{oper=I.SLL, ra=tmpR1, rb=I.IMMop 31, rc=tmpR2});
402 :     mark(I.OPERATE{oper=I.ADDQ, ra=tmpR2, rb=I.REGop tmpR3, rc=rd},an)
403 :     end
404 :     end
405 :     end
406 : monnier 409
407 : george 761
408 : monnier 409 (* emit load immed *)
409 : george 545 and loadConst(c,d,an) = mark(I.LDA{r=d,b=zeroR,d=I.LABop(LE.CONST c)},an)
410 : monnier 409
411 :     (* emit load label *)
412 : monnier 469 and loadLabel(l,d,an) = mark(I.LDA{r=d,b=zeroR,d=I.LABop l},an)
413 : monnier 409
414 :     (* emit a copy *)
415 : monnier 469 and copy(dst,src,an) =
416 : monnier 409 mark(I.COPY{dst=dst,src=src,impl=ref NONE,
417 :     tmp=case dst of
418 :     [_] => NONE | _ => SOME(I.Direct(newReg()))},an)
419 :    
420 :     (* emit a floating point copy *)
421 : monnier 469 and fcopy(dst,src,an) =
422 : monnier 409 mark(I.FCOPY{dst=dst,src=src,impl=ref NONE,
423 :     tmp=case dst of
424 :     [_] => NONE | _ => SOME(I.FDirect(newFreg()))},an)
425 :    
426 : monnier 469 and move(s,d,an) =
427 : leunga 744 if C.sameCell(s,d) orelse C.sameCell(d,zeroR) then () else
428 : monnier 409 mark(I.COPY{dst=[d],src=[s],impl=ref NONE,tmp=NONE},an)
429 :    
430 : monnier 469 and fmove(s,d,an) =
431 : leunga 744 if C.sameCell(s,d) orelse C.sameCell(d,zeroFR) then () else
432 : monnier 409 mark(I.FCOPY{dst=[d],src=[s],impl=ref NONE,tmp=NONE},an)
433 :    
434 :     (* emit an sign extension op *)
435 : monnier 469 and signExt32(r,d) =
436 : leunga 646 emit(I.OPERATE{oper=I.ADDL,ra=r,rb=zeroOpn,rc=d})
437 : monnier 409
438 :     (* emit an commutative arithmetic op *)
439 : monnier 469 and commArith(opcode,a,b,d,an) =
440 : monnier 409 case (opn a,opn b) of
441 :     (I.REGop r,i) => mark(I.OPERATE{oper=opcode,ra=r,rb=i,rc=d},an)
442 :     | (i,I.REGop r) => mark(I.OPERATE{oper=opcode,ra=r,rb=i,rc=d},an)
443 :     | (r,i) => mark(I.OPERATE{oper=opcode,ra=reduceOpn r,rb=i,rc=d},an)
444 :    
445 :     (* emit an arithmetic op *)
446 :     and arith(opcode,a,b,d,an) =
447 :     mark(I.OPERATE{oper=opcode,ra=expr a,rb=opn b,rc=d},an)
448 :     and arith'(opcode,a,b,d,an) =
449 :     let val rb = opn b
450 :     val ra = expr a
451 :     in mark(I.OPERATE{oper=opcode,ra=ra,rb=rb,rc=d},an) end
452 :    
453 :     (* emit a trapping commutative arithmetic op *)
454 :     and commArithTrap(opcode,a,b,d,an) =
455 :     (case (opn a,opn b) of
456 :     (I.REGop r,i) => mark(I.OPERATEV{oper=opcode,ra=r,rb=i,rc=d},an)
457 :     | (i,I.REGop r) => mark(I.OPERATEV{oper=opcode,ra=r,rb=i,rc=d},an)
458 :     | (r,i) => mark(I.OPERATEV{oper=opcode,ra=reduceOpn r,rb=i,rc=d},an);
459 :     emit(I.TRAPB)
460 :     )
461 :    
462 :     (* emit a trapping arithmetic op *)
463 :     and arithTrap(opcode,a,b,d,an) =
464 :     (mark(I.OPERATEV{oper=opcode,ra=expr a,rb=opn b,rc=d},an);
465 :     emit(I.TRAPB)
466 :     )
467 :    
468 :     (* convert an operand into a register *)
469 :     and reduceOpn(I.REGop r) = r
470 :     | reduceOpn(I.IMMop 0) = zeroR
471 :     | reduceOpn opn =
472 :     let val d = newReg()
473 :     in emit(I.OPERATE{oper=I.BIS,ra=zeroR,rb=opn,rc=d}); d end
474 :    
475 :     (* convert an expression into an operand *)
476 :     and opn(T.REG(_,r)) = I.REGop r
477 :     | opn(e as T.LI n) =
478 : george 761 if LE(n, T.I.int_0xff) andalso GE(n, T.I.int_0) then
479 :     I.IMMop(toInt(n))
480 : monnier 409 else let val tmpR = newReg()
481 :     in loadImmed(n,zeroR,tmpR,[]); I.REGop tmpR end
482 : george 545 | opn(T.CONST c) = I.LABop(LE.CONST c)
483 : monnier 409 | opn e = I.REGop(expr e)
484 :    
485 : leunga 583 (* compute base+displacement from an expression
486 :     *)
487 : monnier 409 and addr exp =
488 : leunga 583 let fun toLexp(I.IMMop i) = LE.INT i
489 :     | toLexp(I.LABop le) = le
490 :     | toLexp _ = error "addr.toLexp"
491 : monnier 409
492 : george 761 fun add(n,I.IMMop m) = I.IMMop(toInt n + m)
493 :     | add(n,I.LABop le) = I.LABop(LE.PLUS(LE.INT(toInt(n)),le))
494 : leunga 583 | add(n,_) = error "addr.add"
495 :     fun addC(c,I.IMMop 0) = I.LABop(LE.CONST c)
496 :     | addC(c,disp) = I.LABop(LE.PLUS(LE.CONST c,toLexp disp))
497 :     fun addL(l,I.IMMop 0) = I.LABop l
498 :     | addL(l,disp) = I.LABop(LE.PLUS(l,toLexp disp))
499 : george 761 fun sub(n,I.IMMop m) = I.IMMop(m - toInt n)
500 :     | sub(n,I.LABop le) = I.LABop(LE.MINUS(le,LE.INT(toInt n)))
501 : leunga 583 | sub(n,_) = error "addr.sub"
502 :     fun subC(c,disp) = I.LABop(LE.MINUS(toLexp disp, LE.CONST c))
503 :     fun subL(l,disp) = I.LABop(LE.MINUS(toLexp disp, l))
504 :    
505 :     (* Should really take into account of the address width XXX *)
506 :     fun fold(T.ADD(_,e,T.LI n),disp) = fold(e, add(n,disp))
507 :     | fold(T.ADD(_,e,T.CONST c),disp) = fold(e, addC(c,disp))
508 :     | fold(T.ADD(_,e,T.LABEL l),disp) = fold(e, addL(l,disp))
509 :     | fold(T.ADD(_,T.LI n,e),disp) = fold(e, add(n,disp))
510 :     | fold(T.ADD(_,T.CONST n, e),disp) = fold(e, addC(n,disp))
511 :     | fold(T.ADD(_,T.LABEL l, e),disp) = fold(e, addL(l,disp))
512 :     | fold(T.SUB(_,e,T.LI n),disp) = fold(e, sub(n,disp))
513 :     | fold(T.SUB(_,e,T.CONST n),disp) = fold(e, subC(n,disp))
514 :     | fold(T.SUB(_,e,T.LABEL l),disp) = fold(e, subL(l,disp))
515 :     | fold(e,disp) = (expr e,disp)
516 :    
517 :     in makeEA(fold(exp, zeroImm))
518 :     end
519 :    
520 : monnier 409 (* compute base+displacement+small offset *)
521 :     and offset(base,disp as I.IMMop n,off) =
522 :     let val n' = n+off
523 :     in if literal16 n' then (base,I.IMMop n')
524 :     else
525 :     let val tmp = newReg()
526 :     in emit(I.OPERATE{oper=I.ADDQ,ra=base,rb=disp,rc=tmp});
527 :     (tmp,I.IMMop off)
528 :     end
529 :     end
530 : leunga 583 | offset(base,disp as I.LABop le,off) =
531 :     (base, I.LABop(LE.PLUS(le,LE.INT off)))
532 : monnier 409 | offset(base,disp,off) =
533 :     let val tmp = newReg()
534 :     in emit(I.OPERATE{oper=I.ADDQ,ra=base,rb=disp,rc=tmp});
535 :     (tmp,I.IMMop off)
536 :     end
537 :    
538 : leunga 583 (* check if base offset fits within the field *)
539 :     and makeEA(base, off as I.IMMop offset) =
540 :     if ~32768 <= offset andalso offset <= 32767
541 :     then (base, off)
542 : monnier 409 else
543 :     let val tmpR = newReg()
544 :     (* unsigned low 16 bits *)
545 :     val low = wtoi(Word.andb(itow offset, 0wxffff))
546 :     val high = offset div 65536
547 :     val (lowsgn, highsgn) = (* Sign-extend *)
548 :     if low <= 32767 then (low, high) else (low -65536, high+1)
549 :     in
550 :     (emit(I.LDAH{r=tmpR, b=base, d=I.IMMop highsgn});
551 :     (tmpR, I.IMMop lowsgn))
552 :     end
553 : leunga 583 | makeEA(base, offset) = (base, offset)
554 : monnier 409
555 :     (* look for multiply by 4 and 8 of the given type *)
556 :     and times4or8(ty,e) =
557 : george 761 let
558 :     fun f(t,a,n) = if t = ty then
559 :     if EQ(n, T.I.int_4) then (TIMES4,a)
560 :     else if EQ(n, T.I.int_8) then (TIMES8,a)
561 : monnier 409 else (TIMES1,e)
562 :     else (TIMES1,e)
563 : george 761
564 : monnier 409 fun u(t,a,n) = if t = ty then
565 : george 761 if EQ(n, T.I.int_2) then (TIMES4,a)
566 :     else if EQ(n, T.I.int_3) then (TIMES8,a)
567 : monnier 409 else (TIMES1,e)
568 :     else (TIMES1,e)
569 :     in case e of
570 :     T.MULU(t,a,T.LI n) => f(t,a,n)
571 :     | T.MULS(t,T.LI n,a) => f(t,a,n)
572 :     | T.SLL(t,a,T.LI n) => u(t,a,n)
573 :     | _ => (TIMES1,e)
574 :     end
575 :    
576 :     (* generate an add instruction
577 :     * ***OPT*** look for multiply by 4 and 8 and use the S4ADD and S8ADD
578 :     * forms.
579 :     *)
580 :     and plus(ty,add,s4add,s8add,a,b,d,an) =
581 :     (case times4or8(ty,a) of
582 :     (TIMES4,a) => arith(s4add,a,b,d,an)
583 :     | (TIMES8,a) => arith(s8add,a,b,d,an)
584 :     | _ =>
585 :     case times4or8(ty,b) of
586 :     (TIMES4,b) => arith'(s4add,b,a,d,an)
587 :     | (TIMES8,b) => arith'(s8add,b,a,d,an)
588 :     | _ => commArith(add,a,b,d,an)
589 :     )
590 :    
591 :     (* generate a subtract instruction
592 :     * ***OPT*** look for multiply by 4 and 8
593 :     *)
594 :     and minus(ty,sub,s4sub,s8sub,a,b,d,an) =
595 :     (case times4or8(ty,a) of
596 :     (TIMES4,a) => arith(s4sub,a,b,d,an)
597 :     | (TIMES8,a) => arith(s8sub,a,b,d,an)
598 :     | _ =>
599 : monnier 429 if ty = 64 then
600 : monnier 409 (case b of
601 :     (* use LDA to handle subtraction when possible
602 :     * Note: this may have sign extension problems later.
603 :     *)
604 : george 761 T.LI i => (loadImmed(T.I.NEGT(32,i),expr a,d,an) handle _ =>
605 : monnier 409 arith(sub,a,b,d,an))
606 :     | _ => arith(sub,a,b,d,an)
607 : monnier 429 ) else arith(sub,a,b,d,an)
608 : monnier 409 )
609 :    
610 :     (* look for special constants *)
611 : george 761 and wordOpn(T.LI n) = SOME(T.I.toWord32(32, n))
612 : monnier 409 | wordOpn e = NONE
613 :    
614 : monnier 429 (* look for special byte mask constants
615 :     * IMPORTANT: we must ALWAYS keep the sign bit!
616 :     *)
617 :     and byteMask(_,SOME 0wx00000000) = 0xff
618 :     | byteMask(_,SOME 0wx000000ff) = 0xfe
619 :     | byteMask(_,SOME 0wx0000ff00) = 0xfd
620 :     | byteMask(_,SOME 0wx0000ffff) = 0xfc
621 :     | byteMask(_,SOME 0wx00ff0000) = 0xfb
622 :     | byteMask(_,SOME 0wx00ff00ff) = 0xfa
623 :     | byteMask(_,SOME 0wx00ffff00) = 0xf9
624 :     | byteMask(_,SOME 0wx00ffffff) = 0xf8
625 :     | byteMask(ty,SOME 0wxff000000) = if ty = 64 then 0xf7 else 0x07
626 :     | byteMask(ty,SOME 0wxff0000ff) = if ty = 64 then 0xf6 else 0x06
627 :     | byteMask(ty,SOME 0wxff00ff00) = if ty = 64 then 0xf5 else 0x05
628 :     | byteMask(ty,SOME 0wxff00ffff) = if ty = 64 then 0xf4 else 0x04
629 :     | byteMask(ty,SOME 0wxffff0000) = if ty = 64 then 0xf3 else 0x03
630 :     | byteMask(ty,SOME 0wxffff00ff) = if ty = 64 then 0xf2 else 0x02
631 :     | byteMask(ty,SOME 0wxffffff00) = if ty = 64 then 0xf1 else 0x01
632 :     | byteMask(ty,SOME 0wxffffffff) = if ty = 64 then 0xf0 else 0x00
633 :     | byteMask _ = ~1
634 : monnier 409
635 :     (* generate an and instruction
636 :     * look for special masks.
637 :     *)
638 :     and andb(ty,a,b,d,an) =
639 :     case byteMask(ty,wordOpn a) of
640 : monnier 429 ~1 => (case byteMask(ty,wordOpn b) of
641 :     ~1 => commArith(I.AND,a,b,d,an)
642 : george 761 | mask => arith(I.ZAP,a,LI mask,d,an)
643 : monnier 429 )
644 : george 761 | mask => arith(I.ZAP,b,LI mask,d,an)
645 : monnier 409
646 :     (* generate sll/sra/srl *)
647 :     and sll32(a,b,d,an) =
648 :     case wordOpn b of
649 :     SOME 0w0 => doExpr(a,d,an)
650 :     | SOME 0w1 =>
651 :     let val r = T.REG(32,expr a) in arith(I.ADDL,r,r,d,an) end
652 :     | SOME 0w2 => arith(I.S4ADDL,a,zeroT,d,an)
653 :     | SOME 0w3 => arith(I.S8ADDL,a,zeroT,d,an)
654 :     | _ => let val t = newReg()
655 :     in arith(I.SLL,a,b,t,an);
656 :     signExt32(t,d)
657 :     end
658 :    
659 :     and sll64(a,b,d,an) =
660 :     case wordOpn b of
661 :     SOME 0w0 => doExpr(a,d,an)
662 :     | SOME 0w1 =>
663 :     let val r = T.REG(64,expr a) in arith(I.ADDQ,r,r,d,an) end
664 :     | SOME 0w2 => arith(I.S4ADDQ,a,zeroT,d,an)
665 :     | SOME 0w3 => arith(I.S8ADDQ,a,zeroT,d,an)
666 :     | _ => arith(I.SLL,a,b,d,an)
667 :    
668 :     and sra32(a,b,d,an) =
669 :     let val ra = expr a
670 :     val rb = opn b
671 :     val t = newReg()
672 : monnier 475 in (* On the alpha, all 32 bit values are already sign extended.
673 :     * So no sign extension is necessary.
674 :     * signExt32(ra,t);
675 :     * mark(I.OPERATE{oper=I.SRA,ra=t,rb=rb,rc=d},an)
676 :     *)
677 :     mark(I.OPERATE{oper=I.SRA,ra=ra,rb=rb,rc=d},an)
678 : monnier 409 end
679 :    
680 :     and sra64(a,b,d,an) =
681 :     mark(I.OPERATE{oper=I.SRA,ra=expr a,rb=opn b,rc=d},an)
682 :    
683 :     and srl32(a,b,d,an) =
684 :     let val ra = expr a
685 :     val rb = opn b
686 :     val t = newReg()
687 :     in emit(I.OPERATE{oper=I.ZAP,ra=ra,rb=I.IMMop 0xf0,rc=t});
688 :     mark(I.OPERATE{oper=I.SRL,ra=t,rb=rb,rc=d},an)
689 :     end
690 :    
691 :     and srl64(a,b,d,an) =
692 :     mark(I.OPERATE{oper=I.SRL,ra=expr a,rb=opn b,rc=d},an)
693 :    
694 :     (*
695 :     * Generic multiply.
696 :     * We first try to use the multiply by constant heuristic
697 :     *)
698 :     and multiply(ty,gen,genConst,e1,e2,rd,trapb,an) =
699 :     let fun nonconst(e1,e2) =
700 :     let val instr =
701 :     case (opn e1,opn e2) of
702 :     (i,I.REGop r) => gen{ra=r,rb=i,rc=rd}
703 :     | (I.REGop r,i) => gen{ra=r,rb=i,rc=rd}
704 :     | (r,i) => gen{ra=reduceOpn r,rb=i,rc=rd}
705 :     in mark'(instr,an)::trapb end
706 :     fun const(e,i) =
707 :     let val r = expr e
708 : george 761 in if !useMultByConst andalso
709 :     GE(i, T.I.int_0) andalso
710 :     LT(i, T.I.int_0x100) then
711 :     mark'(gen{ra=r,rb=I.IMMop(toInt i),rc=rd},an)::trapb
712 : monnier 409 else
713 : george 761 (genConst{r=r,i=toInt i,d=rd}@trapb
714 : monnier 409 handle _ => nonconst(T.REG(ty,r),T.LI i))
715 :     end
716 :     val instrs =
717 : george 761 case (e1, e2)
718 :     of (_, T.LI i) => const(e1, i)
719 :     | (T.LI i, _) => const(e2, i)
720 :     | _ => nonconst(e1, e2)
721 : monnier 409 in app emit instrs
722 :     end
723 :    
724 :     (* Round r towards zero.
725 :     * I generate the following sequence of code, which should get
726 :     * mapped into conditional moves.
727 :     *
728 :     * d <- r + i;
729 :     * d <- if (r > 0) then r else d
730 :     *)
731 : george 545 (*
732 : monnier 409 and roundToZero{ty,r,i,d} =
733 :     (doStmt(T.MV(ty,d,T.ADD(ty,T.REG(ty,r),T.LI i)));
734 :     doStmt(T.MV(ty,d,T.COND(ty,T.CMP(ty,T.GE,T.REG(ty,r),T.LI 0),
735 :     T.REG(ty,r),T.REG(ty,d))))
736 :     )
737 : george 545 *)
738 : monnier 409
739 :     (*
740 :     * Generic division.
741 :     * We first try to use the division by constant heuristic
742 :     *)
743 :     and divide(ty,pseudo,genDiv,e1,e2,rd,an) =
744 :     let fun nonconst(e1,e2) =
745 :     pseudo({ra=expr e1,rb=opn e2,rc=rd},reduceOpn)
746 :    
747 :     fun const(e,i) =
748 :     let val r = expr e
749 : george 545 in genDiv{mode=T.TO_ZERO,stm=doStmt}
750 : george 761 {r=r,i=toInt i,d=rd}
751 : monnier 409 handle _ => nonconst(T.REG(ty,r),T.LI i)
752 :     end
753 :     val instrs =
754 :     case e2 of
755 :     T.LI i => const(e1,i)
756 :     | _ => nonconst(e1,e2)
757 :     in app emit instrs
758 :     end
759 :    
760 :    
761 :     (*
762 :     and multTrap(MULV,ADD,ADDV,e1,e2,rd,an) = (* signed multiply and trap *)
763 :     let val ADD = fn {ra,rb,rc} => I.OPERATE{oper=ADD,ra=ra,rb=rb,rc=rc}
764 :     val ADDV = fn {ra,rb,rc} => I.OPERATEV{oper=ADDV,ra=ra,rb=rb,rc=rc}
765 :     val MULV = fn {ra,rb,rc} => I.OPERATEV{oper=MULV,ra=ra,rb=rb,rc=rc}
766 :     in multiply(MULV,ADD,ADDV,e1,e2,rd,an);
767 :     emit(I.TRAPB)
768 :     end
769 :    
770 :     and mulu(MUL,ADD,e1,e2,rd,an) = (* unsigned multiply *)
771 :     let val ADD = fn {ra,rb,rc} => I.OPERATE{oper=ADD,ra=ra,rb=rb,rc=rc}
772 :     val MUL = fn {ra,rb,rc} => I.OPERATE{oper=MUL,ra=ra,rb=rb,rc=rc}
773 :     in multiply(MUL,ADD,ADD,e1,e2,rd,an)
774 :     end
775 :    
776 :     (* Multiplication *)
777 :     and multiply(MULV, ADD, ADDV, e1, e2, rd, an) =
778 :     let val reg = expr e1
779 :     val opn = opn e2
780 :     fun emitMulvImmed (reg, 0, rd) =
781 :     emit(I.LDA{r=rd, b=zeroR, d=I.IMMop 0})
782 :     | emitMulvImmed (reg, 1, rd) =
783 :     emit(ADD{ra=reg, rb=zeroOpn, rc=rd})
784 :     | emitMulvImmed (reg, multiplier, rd) =
785 :     let fun log2 0w1 = 0 | log2 n = 1 + (log2 (Word.>> (n, 0w1)))
786 :     fun exp2 n = Word.<<(0w1, n)
787 :     fun bitIsSet (x,n) = Word.andb(x,exp2 n) <> 0w0
788 :     fun loop (~1) = ()
789 :     | loop n =
790 :     (if bitIsSet(itow multiplier, itow n) then
791 :     emit(ADDV{ra=reg,rb=I.REGop rd,rc=rd})
792 :     else ();
793 :     if n>0 then
794 :     emit(ADDV{ra=rd,rb=I.REGop rd,rc=rd})
795 :     else ();
796 :     loop (n-1))
797 :     in emit(ADDV{ra=reg, rb=I.REGop reg, rc=rd});
798 :     loop ((log2 (itow multiplier)) - 1)
799 :     end
800 :     in case opn of
801 :     (I.IMMop multiplier) => emitMulvImmed (reg, multiplier, rd)
802 :     | _ => mark(MULV{ra=reg, rb=opn, rc=rd},an)
803 :     (*esac*)
804 :     end
805 :     *)
806 :    
807 :     (* generate pseudo instruction *)
808 :     and pseudo(instr,e1,e2,rc) =
809 :     app emit (instr({ra=expr e1,rb=opn e2,rc=rc}, reduceOpn))
810 :    
811 :     (* generate a load *)
812 :     and load(ldOp,ea,d,mem,an) =
813 :     let val (base,disp) = addr ea
814 :     in mark(I.LOAD{ldOp=ldOp,r=d,b=base,d=disp,mem=mem},an) end
815 :    
816 :     (* generate a load with zero extension *)
817 :     and loadZext(ea,rd,mem,EXT,an) =
818 :     let val (b, d) = addr ea
819 :     val t1 = newReg()
820 :     val _ = mark(I.LOAD{ldOp=I.LDQ_U, r=t1, b=b, d=d, mem=mem},an);
821 :     val t2 = lda(b,d)
822 :     in emit(I.OPERATE{oper=EXT, ra=t1, rb=I.REGop t2, rc=rd}) end
823 :    
824 :     (* generate a load with sign extension *)
825 :     and loadSext(ea,rd,mem,off,EXT,shift,an) =
826 :     let val (b, d) = addr ea
827 :     val (b',d') = offset(b,d,off)
828 :     val t1 = newReg()
829 :     val t2 = newReg()
830 :     val t3 = newReg()
831 :     in mark(I.LOAD{ldOp=I.LDQ_U, r=t1, b=b, d=d, mem=mem},an);
832 :     emit(I.LDA{r=t2, b=b', d=d'});
833 :     emit(I.OPERATE{oper=EXT, ra=t1, rb=I.REGop t2, rc=t3});
834 :     emit(I.OPERATE{oper=I.SRA, ra=t3, rb=I.IMMop shift, rc=rd})
835 :     end
836 :    
837 :     (* generate a load byte with zero extension (page 4-48) *)
838 : leunga 583 and load8(ea,rd,mem,an) =
839 :     if !byteWordLoadStores then load(I.LDBU,ea,rd,mem,an)
840 :     else loadZext(ea,rd,mem,I.EXTBL,an)
841 : monnier 409
842 :     (* generate a load byte with sign extension (page 4-48) *)
843 : leunga 583 and load8s(ea,rd,mem,an) =
844 : leunga 585 if !byteWordLoadStores then load(I.LDB,ea,rd,mem,an)
845 : leunga 583 else loadSext(ea,rd,mem,1,I.EXTQH,56,an)
846 : monnier 409
847 :     (* generate a load 16 bit *)
848 : leunga 583 and load16(ea,rd,mem,an) =
849 :     if !byteWordLoadStores then load(I.LDWU,ea,rd,mem,an)
850 :     else loadZext(ea,rd,mem,I.EXTWL,an)
851 : monnier 409
852 :     (* generate a load 16 bit with sign extension *)
853 : leunga 583 and load16s(ea,rd,mem,an) =
854 : leunga 585 if !byteWordLoadStores then load(I.LDW,ea,rd,mem,an)
855 : leunga 583 else loadSext(ea,rd,mem,2,I.EXTQH,48,an)
856 : monnier 409
857 :     (* generate a load 32 bit with sign extension *)
858 :     and load32s(ea,rd,mem,an) = load(I.LDL,ea,rd,mem,an)
859 :    
860 :     (* generate a floating point load *)
861 :     and fload(ldOp,ea,d,mem,an) =
862 :     let val (base,disp) = addr ea
863 :     in mark(I.FLOAD{ldOp=ldOp,r=d,b=base,d=disp,mem=mem},an) end
864 :    
865 :     (* generate a store *)
866 :     and store(stOp,ea,data,mem,an) =
867 :     let val (base,disp) = addr ea
868 :     in mark(I.STORE{stOp=stOp,r=expr data,b=base,d=disp,mem=mem},an) end
869 :    
870 :     (* generate an store8 or store16 *)
871 :     and storeUnaligned(ea,data,mem,INS,MSK,an) =
872 :     let val (base,disp) = addr ea
873 :     val data = expr data
874 :     val t1 = newReg()
875 :     val t3 = newReg()
876 :     val t4 = newReg()
877 :     val t5 = newReg()
878 :     val _ = emit(I.LOAD{ldOp=I.LDQ_U, r=t1, b=base, d=disp, mem=mem})
879 :     val t2 = lda(base,disp)
880 :     in emit(I.OPERATE{oper=INS, ra=data, rb=I.REGop(t2), rc=t3});
881 :     emit(I.OPERATE{oper=MSK, ra=t1, rb=I.REGop(t2), rc=t4});
882 :     emit(I.OPERATE{oper=I.BIS, ra=t4, rb=I.REGop(t3), rc=t5});
883 :     mark(I.STORE{stOp=I.STQ_U, r=t5, b=base, d=disp, mem=mem},an)
884 :     end
885 :    
886 :     (* generate a store byte *)
887 :     and store8(ea,data,mem,an) =
888 : leunga 585 if !byteWordLoadStores then store(I.STB, ea, data, mem, an)
889 :     else storeUnaligned(ea,data,mem,I.INSBL,I.MSKBL,an)
890 : monnier 409
891 :     (* generate a store16 *)
892 :     and store16(ea,data,mem,an) =
893 : leunga 585 if !byteWordLoadStores then store(I.STW, ea, data, mem, an)
894 :     else storeUnaligned(ea,data,mem,I.INSWL,I.MSKWL,an)
895 : monnier 409
896 : monnier 429 (* generate conversion from floating point to integer *)
897 :     and cvtf2i(pseudo,rounding,e,rd,an) =
898 :     app emit (pseudo{mode=rounding, fs=fexpr e, rd=rd})
899 :    
900 : monnier 409 (* generate an expression and return the register that holds the result *)
901 : george 761 and expr(e) = let
902 :     fun comp() = let
903 :     val r = newReg()
904 :     in doExpr(e, r, []); r
905 :     end
906 :     in
907 :     case e
908 :     of T.REG(_, r) => r
909 :     | T.LI z => if T.I.isZero(z) then zeroR else comp()
910 : leunga 624 (* On the alpha: all 32 bit values are already sign extended.
911 :     * So no sign extension is necessary
912 :     *)
913 : george 761 | T.SX(64, 32, e) => expr e
914 :     | T.ZX(64, 32, e) => expr e
915 :     | _ => comp()
916 :     end
917 : leunga 624
918 : monnier 409 (* generate an expression that targets register d *)
919 : monnier 429 and doExpr(exp,d,an) =
920 :     case exp of
921 : monnier 409 T.REG(_,r) => move(r,d,an)
922 :     | T.LI n => loadImmed(n,zeroR,d,an)
923 :     | T.LABEL l => loadLabel(l,d,an)
924 :     | T.CONST c => loadConst(c,d,an)
925 :    
926 :     (* special optimizations for additions and subtraction
927 :     * Question: using LDA for all widths is not really correct
928 :     * since the result may not fit into the sign extension scheme.
929 :     *)
930 : monnier 429 | T.ADD(64,e,T.LABEL le) => mark(I.LDA{r=d,b=expr e,d=I.LABop le},an)
931 :     | T.ADD(64,T.LABEL le,e) => mark(I.LDA{r=d,b=expr e,d=I.LABop le},an)
932 : george 545 | T.ADD(64,e,T.CONST c) =>
933 :     mark(I.LDA{r=d,b=expr e,d=I.LABop(LE.CONST c)},an)
934 :     | T.ADD(64,T.CONST c,e) =>
935 :     mark(I.LDA{r=d,b=expr e,d=I.LABop(LE.CONST c)},an)
936 : monnier 429 | T.ADD(64,e,T.LI i) => loadImmed(i, expr e, d, an)
937 :     | T.ADD(64,T.LI i,e) => loadImmed(i, expr e, d, an)
938 : george 761 | T.SUB(sz, a, b as T.LI z) =>
939 :     if T.I.isZero(z) then
940 :     doExpr(a,d,an)
941 :     else (case sz
942 :     of 32 => minus(32,I.SUBL,I.S4SUBL,I.S8SUBL,a,b,d,an)
943 :     | 64 => minus(64,I.SUBQ,I.S4SUBQ,I.S8SUBQ,a,b,d,an)
944 :     | _ => doExpr(Gen.compileRexp exp,d,an)
945 :     (*esac*))
946 : monnier 409
947 :     (* 32-bit support *)
948 :     | T.ADD(32,a,b) => plus(32,I.ADDL,I.S4ADDL,I.S8ADDL,a,b,d,an)
949 :     | T.SUB(32,a,b) => minus(32,I.SUBL,I.S4SUBL,I.S8SUBL,a,b,d,an)
950 :     | T.ADDT(32,a,b) => commArithTrap(I.ADDLV,a,b,d,an)
951 :     | T.SUBT(32,a,b) => arithTrap(I.SUBLV,a,b,d,an)
952 : monnier 429 | T.MULT(32,a,b) =>
953 : monnier 409 multiply(32,
954 :     fn{ra,rb,rc} => I.OPERATEV{oper=I.MULLV,ra=ra,rb=rb,rc=rc},
955 :     Mult32.multiply,a,b,d,trapb,an)
956 : monnier 429 | T.MULU(32,a,b) =>
957 : monnier 409 multiply(32,
958 :     fn{ra,rb,rc} => I.OPERATE{oper=I.MULL,ra=ra,rb=rb,rc=rc},
959 :     Mulu32.multiply,a,b,d,[],an)
960 : monnier 429 | T.MULS(32,a,b) =>
961 :     multiply(32,
962 :     fn{ra,rb,rc} => I.OPERATE{oper=I.MULL,ra=ra,rb=rb,rc=rc},
963 :     Muls32.multiply,a,b,d,[],an)
964 :     | T.DIVT(32,a,b) => divide(32,P.divlv,Mult32.divide,a,b,d,an)
965 :     | T.DIVU(32,a,b) => divide(32,P.divlu,Mulu32.divide,a,b,d,an)
966 :     | T.DIVS(32,a,b) => divide(32,P.divl,Muls32.divide,a,b,d,an)
967 :     | T.REMT(32,a,b) => pseudo(P.remlv,a,b,d)
968 :     | T.REMU(32,a,b) => pseudo(P.remlu,a,b,d)
969 :     | T.REMS(32,a,b) => pseudo(P.reml,a,b,d)
970 :    
971 : monnier 409 | T.SLL(32,a,b) => sll32(a,b,d,an)
972 :     | T.SRA(32,a,b) => sra32(a,b,d,an)
973 :     | T.SRL(32,a,b) => srl32(a,b,d,an)
974 :    
975 :     (* 64 bit support *)
976 :     | T.ADD(64,a,b) => plus(64,I.ADDQ,I.S4ADDQ,I.S8ADDQ,a,b,d,an)
977 :     | T.SUB(64,a,b) => minus(64,I.SUBQ,I.S4SUBQ,I.S8SUBQ,a,b,d,an)
978 :     | T.ADDT(64,a,b) => commArithTrap(I.ADDQV,a,b,d,an)
979 :     | T.SUBT(64,a,b) => arithTrap(I.SUBQV,a,b,d,an)
980 : monnier 429 | T.MULT(64,a,b) =>
981 : monnier 409 multiply(64,
982 :     fn{ra,rb,rc} => I.OPERATEV{oper=I.MULQV,ra=ra,rb=rb,rc=rc},
983 :     Mult64.multiply,a,b,d,trapb,an)
984 : monnier 429 | T.MULU(64,a,b) =>
985 : monnier 409 multiply(64,
986 :     fn{ra,rb,rc} => I.OPERATE{oper=I.MULQ,ra=ra,rb=rb,rc=rc},
987 :     Mulu64.multiply,a,b,d,[],an)
988 : monnier 429 | T.MULS(64,a,b) =>
989 :     multiply(64,
990 :     fn{ra,rb,rc} => I.OPERATE{oper=I.MULQ,ra=ra,rb=rb,rc=rc},
991 :     Muls64.multiply,a,b,d,[],an)
992 :     | T.DIVT(64,a,b) => divide(64,P.divqv,Mult64.divide,a,b,d,an)
993 :     | T.DIVU(64,a,b) => divide(64,P.divqu,Mulu64.divide,a,b,d,an)
994 :     | T.DIVS(64,a,b) => divide(64,P.divq,Muls64.divide,a,b,d,an)
995 :     | T.REMT(64,a,b) => pseudo(P.remqv,a,b,d)
996 :     | T.REMU(64,a,b) => pseudo(P.remqu,a,b,d)
997 :     | T.REMS(64,a,b) => pseudo(P.remq,a,b,d)
998 :    
999 : monnier 409 | T.SLL(64,a,b) => sll64(a,b,d,an)
1000 :     | T.SRA(64,a,b) => sra64(a,b,d,an)
1001 :     | T.SRL(64,a,b) => srl64(a,b,d,an)
1002 :    
1003 :     (* special bit operations with complement *)
1004 :     | T.ANDB(_,a,T.NOTB(_,b)) => arith(I.BIC,a,b,d,an)
1005 :     | T.ORB(_,a,T.NOTB(_,b)) => arith(I.ORNOT,a,b,d,an)
1006 :     | T.XORB(_,a,T.NOTB(_,b)) => commArith(I.EQV,a,b,d,an)
1007 :     | T.ANDB(_,T.NOTB(_,a),b) => arith(I.BIC,b,a,d,an)
1008 :     | T.ORB(_,T.NOTB(_,a),b) => arith(I.ORNOT,b,a,d,an)
1009 :     | T.XORB(_,T.NOTB(_,a),b) => commArith(I.EQV,b,a,d,an)
1010 :     | T.NOTB(_,T.XORB(_,a,b)) => commArith(I.EQV,b,a,d,an)
1011 :    
1012 :     (* bit operations *)
1013 :     | T.ANDB(ty,a,b) => andb(ty,a,b,d,an)
1014 :     | T.XORB(_,a,b) => commArith(I.XOR,a,b,d,an)
1015 :     | T.ORB(_,a,b) => commArith(I.BIS,a,b,d,an)
1016 :     | T.NOTB(_,e) => arith(I.ORNOT,zeroT,e,d,an)
1017 :    
1018 :     (* loads *)
1019 : leunga 744 | T.SX(_,_,T.LOAD(8,ea,mem)) => load8s(ea,d,mem,an)
1020 :     | T.SX(_,_,T.LOAD(16,ea,mem))=> load16s(ea,d,mem,an)
1021 :     | T.SX(_,_,T.LOAD(32,ea,mem))=> load32s(ea,d,mem,an)
1022 :     | T.ZX((8|16|32|64),_,T.LOAD(8,ea,mem)) => load8(ea,d,mem,an)
1023 :     | T.ZX((16|32|64),_,T.LOAD(16,ea,mem))=> load16(ea,d,mem,an)
1024 :     | T.ZX(64,_,T.LOAD(64,ea,mem)) => load(I.LDQ,ea,d,mem,an)
1025 : monnier 409 | T.LOAD(8,ea,mem) => load8(ea,d,mem,an)
1026 :     | T.LOAD(16,ea,mem) => load16(ea,d,mem,an)
1027 : monnier 429 | T.LOAD(32,ea,mem) => load32s(ea,d,mem,an)
1028 : monnier 409 | T.LOAD(64,ea,mem) => load(I.LDQ,ea,d,mem,an)
1029 :    
1030 : monnier 429 (* floating -> int conversion *)
1031 : monnier 475 | T.CVTF2I(ty,rounding,fty,e) =>
1032 :     (case (fty,ty) of
1033 : monnier 429 (32,32) => cvtf2i(P.cvtsl,rounding,e,d,an)
1034 :     | (32,64) => cvtf2i(P.cvtsq,rounding,e,d,an)
1035 :     | (64,32) => cvtf2i(P.cvttl,rounding,e,d,an)
1036 :     | (64,64) => cvtf2i(P.cvttq,rounding,e,d,an)
1037 : george 545 | _ => doExpr(Gen.compileRexp exp,d,an) (* other cases *)
1038 : monnier 429 )
1039 :    
1040 : monnier 409 (* conversion to boolean *)
1041 : george 761 | T.COND(_, T.CMP(ty,cond,e1,e2), x, y) =>
1042 :     (case (x, y)
1043 :     of (T.LI n, T.LI m) =>
1044 :     if EQ(n, int_1) andalso EQ(m, int_0) then
1045 :     compare(ty,cond,e1,e2,d,an)
1046 :     else if EQ(n, int_0) andalso EQ(m, int_1) then
1047 :     compare(ty,T.Basis.negateCond cond,e1,e2,d,an)
1048 :     else
1049 :     cmove(ty,cond,e1,e2,x,y,d,an)
1050 :     | _ => cmove(ty,cond,e1,e2,x,y,d,an)
1051 :     (*esac*))
1052 : monnier 409
1053 : george 545 | T.LET(s,e) => (doStmt s; doExpr(e, d, an))
1054 :     | T.MARK(e,A.MARKREG f) => (f d; doExpr(e,d,an))
1055 :     | T.MARK(e,a) => doExpr(e,d,a::an)
1056 : monnier 475 (* On the alpha: all 32 bit values are already sign extended.
1057 :     * So no sign extension is necessary
1058 :     *)
1059 : leunga 744 | T.SX(64, 32, e) => doExpr(e, d, an)
1060 :     | T.ZX(64, 32, e) => doExpr(e, d, an)
1061 : george 545
1062 :     | T.PRED(e, c) => doExpr(e, d, A.CTRLUSE c::an)
1063 : george 555 | T.REXT e => ExtensionComp.compileRext (reducer()) {e=e, an=an, rd=d}
1064 : monnier 429
1065 :     (* Defaults *)
1066 : george 545 | e => doExpr(Gen.compileRexp e,d,an)
1067 : monnier 409
1068 :     (* Hmmm... this is the funky thing described in the comments
1069 :     * in at the top of the file. This should be made parametrizable
1070 :     * for other backends.
1071 :     *)
1072 : george 545 and farith(opcode,opcodeSMLNJ,a,b,d,an) =
1073 : monnier 409 let val fa = fexpr a
1074 :     val fb = fexpr b
1075 : george 545 in if SMLNJfloatingPoint then
1076 :     (emit(I.DEFFREG d);
1077 :     mark(I.FOPERATEV{oper=opcodeSMLNJ,fa=fa,fb=fb,fc=d},an);
1078 :     emit(I.TRAPB)
1079 :     )
1080 :     else mark(I.FOPERATE{oper=opcode,fa=fa,fb=fb,fc=d},an)
1081 : monnier 409 end
1082 :    
1083 : george 545 and farith'(opcode,a,b,d,an) =
1084 :     mark(I.FOPERATE{oper=opcode,fa=fexpr a,fb=fexpr b,fc=d},an)
1085 :    
1086 : monnier 429 and funary(opcode,e,d,an) = mark(I.FUNARY{oper=opcode,fb=fexpr e,fc=d},an)
1087 :    
1088 :    
1089 : monnier 409 (* generate an floating point expression
1090 :     * return the register that holds the result
1091 :     *)
1092 :     and fexpr(T.FREG(_,r)) = r
1093 :     | fexpr e = let val d = newFreg() in doFexpr(e,d,[]); d end
1094 :    
1095 :     (* generate an external floating point operation *)
1096 : monnier 429 and fcvti2f(pseudo,e,fd,an) =
1097 : monnier 409 let val opnd = opn e
1098 : monnier 429 in app emit (pseudo({opnd=opnd, fd=fd}, reduceOpn))
1099 : monnier 409 end
1100 :    
1101 :     (* generate a floating point store *)
1102 :     and fstore(stOp,ea,data,mem,an) =
1103 :     let val (base,disp) = addr ea
1104 :     in mark(I.FSTORE{stOp=stOp,r=fexpr data,b=base,d=disp,mem=mem},an)
1105 :     end
1106 :    
1107 :     (* generate a floating point expression that targets register d *)
1108 :     and doFexpr(e,d,an) =
1109 :     case e of
1110 :     T.FREG(_,f) => fmove(f,d,an)
1111 :    
1112 :     (* single precision support *)
1113 : george 545 | T.FADD(32,a,b) => farith(I.ADDS,ADDSX,a,b,d,an)
1114 :     | T.FSUB(32,a,b) => farith(I.SUBS,SUBSX,a,b,d,an)
1115 :     | T.FMUL(32,a,b) => farith(I.MULS,MULSX,a,b,d,an)
1116 :     | T.FDIV(32,a,b) => farith(I.DIVS,DIVSX,a,b,d,an)
1117 : monnier 409
1118 :     (* double precision support *)
1119 : george 545 | T.FADD(64,a,b) => farith(I.ADDT,ADDTX,a,b,d,an)
1120 :     | T.FSUB(64,a,b) => farith(I.SUBT,SUBTX,a,b,d,an)
1121 :     | T.FMUL(64,a,b) => farith(I.MULT,MULTX,a,b,d,an)
1122 :     | T.FDIV(64,a,b) => farith(I.DIVT,DIVTX,a,b,d,an)
1123 : monnier 409
1124 : george 545 (* copy sign (correct?) XXX *)
1125 :     | T.FCOPYSIGN(_,T.FNEG(_,a),b) => farith'(I.CPYSN,a,b,d,an)
1126 :     | T.FCOPYSIGN(_,a,T.FNEG(_,b)) => farith'(I.CPYSN,a,b,d,an)
1127 :     | T.FNEG(_,T.FCOPYSIGN(_,a,b)) => farith'(I.CPYSN,a,b,d,an)
1128 :     | T.FCOPYSIGN(_,a,b) => farith'(I.CPYS,a,b,d,an)
1129 : monnier 429
1130 : monnier 409 (* generic *)
1131 :     | T.FABS(_,a) =>
1132 :     mark(I.FOPERATE{oper=I.CPYS,fa=zeroFR,fb=fexpr a,fc=d},an)
1133 :     | T.FNEG(_,a) =>
1134 :     let val fs = fexpr a
1135 :     in mark(I.FOPERATE{oper=I.CPYSN,fa=fs,fb=fs,fc=d},an) end
1136 :     | T.FSQRT(_,a) => error "fsqrt"
1137 :    
1138 :     (* loads *)
1139 :     | T.FLOAD(32,ea,mem) => fload(I.LDS,ea,d,mem,an)
1140 :     | T.FLOAD(64,ea,mem) => fload(I.LDT,ea,d,mem,an)
1141 : monnier 429
1142 :     (* floating/floating conversion
1143 :     * Note: it is not necessary to convert single precision
1144 :     * to double on the alpha.
1145 :     *)
1146 : george 545 | T.CVTF2F(fty,fty',e) => (* ignore rounding mode for now *)
1147 : monnier 475 (case (fty,fty') of
1148 : monnier 429 (64,64) => doFexpr(e,d,an)
1149 :     | (64,32) => doFexpr(e,d,an)
1150 :     | (32,32) => doFexpr(e,d,an)
1151 :     | (32,64) => funary(I.CVTTS,e,d,an) (* use normal rounding *)
1152 :     | _ => error "CVTF2F"
1153 :     )
1154 : monnier 409
1155 : monnier 429 (* integer -> floating point conversion *)
1156 : george 545 | T.CVTI2F(fty,ty,e) =>
1157 : monnier 429 let val pseudo =
1158 : monnier 475 case (ty,fty) of
1159 : monnier 429 (ty,32) => if ty <= 32 then P.cvtls else P.cvtqs
1160 :     | (ty,64) => if ty <= 32 then P.cvtlt else P.cvtqt
1161 :     | _ => error "CVTI2F"
1162 :     in fcvti2f(pseudo,e,d,an) end
1163 :    
1164 : george 545 | T.FMARK(e,A.MARKREG f) => (f d; doFexpr(e,d,an))
1165 :     | T.FMARK(e,a) => doFexpr(e,d,a::an)
1166 :     | T.FPRED(e,c) => doFexpr(e, d, A.CTRLUSE c::an)
1167 : george 555 | T.FEXT e => ExtensionComp.compileFext (reducer()) {e=e, fd=d, an=an}
1168 : monnier 409 | _ => error "doFexpr"
1169 :    
1170 :     (* check whether an expression is andb(e,1) *)
1171 : george 761 and isAndb1(e as T.ANDB(_, e1, e2)) = let
1172 :     fun isOne(n, ei) =
1173 :     if EQ(n, int_1) then (true, ei) else (false, e)
1174 :     in
1175 :     case(e1, e2)
1176 :     of (T.LI n, _) => isOne(n, e2)
1177 :     | (_, T.LI n) => isOne(n, e1)
1178 :     | _ => (false, e)
1179 :     end
1180 :     | isAndb1 e = (false, e)
1181 : monnier 409
1182 : george 761 and zeroOrOne(T.LI n) =
1183 :     if T.I.isZero n then ZERO
1184 :     else if EQ(n, int_1) then ONE
1185 :     else OTHER
1186 :     | zeroOrOne _ = OTHER
1187 : monnier 409
1188 :     (* compile a branch *)
1189 : george 545 and branch(e,lab,an) =
1190 : monnier 409 case e of
1191 :     T.CMP(ty,cc,e1 as T.LI _,e2) =>
1192 : george 545 branchBS(ty,T.Basis.swapCond cc,e2,e1,lab,an)
1193 : monnier 409 | T.CMP(ty,cc,e1,e2) => branchBS(ty,cc,e1,e2,lab,an)
1194 : george 545 (* generate an floating point branch *)
1195 :     | T.FCMP(fty,cc,e1,e2) =>
1196 :     let val f1 = fexpr e1
1197 :     val f2 = fexpr e2
1198 :     fun bcc(cmp,br) =
1199 :     let val tmpR = C.newFreg()
1200 :     in emit(I.DEFFREG(tmpR));
1201 :     emit(I.FOPERATE{oper=cmp,fa=f1,fb=f2,fc=tmpR});
1202 :     emit(I.TRAPB);
1203 :     mark(I.FBRANCH{b=br,f=tmpR,lab=lab},an)
1204 :     end
1205 :     fun fall(cmp1, br1, cmp2, br2) =
1206 :     let val tmpR1 = newFreg()
1207 :     val tmpR2 = newFreg()
1208 :     val fallLab = Label.newLabel ""
1209 :     in emit(I.DEFFREG(tmpR1));
1210 :     emit(I.FOPERATE{oper=cmp1, fa=f1, fb=f2, fc=tmpR1});
1211 :     emit(I.TRAPB);
1212 :     mark(I.FBRANCH{b=br1, f=tmpR1, lab=fallLab},an);
1213 :     emit(I.DEFFREG(tmpR2));
1214 :     emit(I.FOPERATE{oper=cmp2, fa=f1, fb=f2, fc=tmpR2});
1215 :     emit(I.TRAPB);
1216 :     mark(I.FBRANCH{b=br2, f=tmpR2, lab=lab},an);
1217 :     defineLabel fallLab
1218 :     end
1219 :     fun bcc2(cmp1, br1, cmp2, br2) =
1220 :     (bcc(cmp1, br1); bcc(cmp2, br2))
1221 :     in case cc of
1222 :     T.== => bcc(I.CMPTEQSU, I.FBNE)
1223 :     | T.?<> => bcc(I.CMPTEQSU, I.FBEQ)
1224 :     | T.? => bcc(I.CMPTUNSU, I.FBNE)
1225 :     | T.<=> => bcc(I.CMPTUNSU, I.FBEQ)
1226 :     | T.> => fall(I.CMPTLESU, I.FBNE, I.CMPTUNSU, I.FBEQ)
1227 :     | T.>= => fall(I.CMPTLTSU, I.FBNE, I.CMPTUNSU, I.FBEQ)
1228 :     | T.?> => bcc(I.CMPTLESU, I.FBEQ)
1229 :     | T.?>= => bcc(I.CMPTLTSU, I.FBEQ)
1230 :     | T.< => bcc(I.CMPTLTSU, I.FBNE)
1231 :     | T.<= => bcc(I.CMPTLESU, I.FBNE)
1232 :     | T.?< => bcc2(I.CMPTLTSU, I.FBNE, I.CMPTUNSU, I.FBNE)
1233 : leunga 744 | T.?<= => bcc2(I.CMPTLESU, I.FBNE, I.CMPTUNSU, I.FBNE)
1234 :     | T.<> => fall(I.CMPTEQSU, I.FBNE, I.CMPTUNSU, I.FBEQ)
1235 :     | T.?= => bcc2(I.CMPTEQSU, I.FBNE, I.CMPTUNSU, I.FBNE)
1236 :     | _ => error "branch"
1237 : george 545 end
1238 :     | e => mark(I.BRANCH{b=I.BNE,r=ccExpr e,lab=lab},an)
1239 : monnier 409
1240 : george 545 and br(opcode,exp,lab,an) = mark(I.BRANCH{b=opcode,r=expr exp,lab=lab},an)
1241 : monnier 409
1242 :     (* Use the branch on bit set/clear instruction when possible *)
1243 :     and branchBS(ty,cc,a,b,lab,an) =
1244 :     (case (cc,isAndb1 a,zeroOrOne b) of
1245 :     (T.EQ,(true,e),ONE) => br(I.BLBS,e,lab,an)
1246 :     | (T.EQ,(true,e),ZERO) => br(I.BLBC,e,lab,an)
1247 :     | (T.NE,(true,e),ZERO) => br(I.BLBS,e,lab,an)
1248 :     | (T.NE,(true,e),ONE) => br(I.BLBC,e,lab,an)
1249 :     | (cc,_,_) => branchIt(ty,cc,a,b,lab,an)
1250 :     )
1251 :    
1252 :     (* generate a branch instruction.
1253 :     * Check for branch on zero as a special case
1254 :     *)
1255 : george 761
1256 :     and branchIt(ty,cc,e1,e2 as T.LI z,lab,an) =
1257 :     if T.I.isZero z then branchIt0(cc,e1,lab,an)
1258 :     else branchItOther(ty,cc,e1,e2,lab,an)
1259 : monnier 409 | branchIt(ty,cc,e1,e2,lab,an) = branchItOther(ty,cc,e1,e2,lab,an)
1260 :    
1261 :     (* generate a branch instruction.
1262 :     * This function optimizes the special case of comparison with zero.
1263 :     *)
1264 :     and branchIt0(T.EQ,e,lab,an) = br(I.BEQ,e,lab,an)
1265 :     | branchIt0(T.NE,e,lab,an) = br(I.BNE,e,lab,an)
1266 :     | branchIt0(T.GT,e,lab,an) = br(I.BGT,e,lab,an)
1267 :     | branchIt0(T.GE,e,lab,an) = br(I.BGE,e,lab,an)
1268 :     | branchIt0(T.LE,e,lab,an) = br(I.BLE,e,lab,an)
1269 :     | branchIt0(T.LT,e,lab,an) = br(I.BLT,e,lab,an)
1270 :     | branchIt0(T.GTU,e,lab,an) = br(I.BNE,e,lab,an) (* always > 0! *)
1271 :     | branchIt0(T.GEU,e,lab,an) = (* always true! *) goto(lab,an)
1272 :     | branchIt0(T.LTU,e,lab,an) = (* always false! *) ()
1273 :     | branchIt0(T.LEU,e,lab,an) = br(I.BEQ,e,lab,an) (* never < 0! *)
1274 : leunga 744 | branchIt0 _ = error "brnachIt0"
1275 : monnier 409
1276 :     (* Generate the operands for unsigned comparisons
1277 :     * Mask out high order bits whenever necessary.
1278 :     *)
1279 :     and unsignedCmpOpnds(ty,e1,e2) =
1280 :     let fun zapHi(r,mask) =
1281 :     let val d = newReg()
1282 :     in emit(I.OPERATE{oper=I.ZAP, ra=r, rb=I.IMMop mask,rc=d});
1283 :     I.REGop d
1284 :     end
1285 :    
1286 :     fun zap(opn as I.REGop r) =
1287 :     (case ty of
1288 :     8 => zapHi(r,0xfd)
1289 :     | 16 => zapHi(r,0xfc)
1290 :     | 32 => zapHi(r,0xf0)
1291 :     | 64 => opn
1292 :     | _ => error "unsignedCmpOpnds"
1293 :     )
1294 :     | zap opn = opn
1295 :     val opn1 = opn e1
1296 :     val opn2 = opn e2
1297 :     in (zap opn1,zap opn2) end
1298 :    
1299 :     (* Generate a branch *)
1300 :     and branchItOther(ty,cond,e1,e2,lab,an) =
1301 :     let val tmpR = newReg()
1302 :     fun signedCmp(cmp,br) =
1303 :     (emit(I.OPERATE{oper=cmp, ra=expr e1, rb=opn e2, rc=tmpR});
1304 : george 545 mark(I.BRANCH{b=br, r=tmpR, lab=lab},an)
1305 : monnier 409 )
1306 :     fun unsignedCmp(ty,cmp,br) =
1307 :     let val (x,y) = unsignedCmpOpnds(ty,e1,e2)
1308 :     in emit(I.OPERATE{oper=cmp,ra=reduceOpn x,rb=y,rc=tmpR});
1309 : george 545 mark(I.BRANCH{b=br, r=tmpR, lab=lab},an)
1310 : monnier 409 end
1311 :     in case cond of
1312 :     T.LT => signedCmp(I.CMPLT,I.BNE)
1313 :     | T.LE => signedCmp(I.CMPLE,I.BNE)
1314 :     | T.GT => signedCmp(I.CMPLE,I.BEQ)
1315 :     | T.GE => signedCmp(I.CMPLT,I.BEQ)
1316 :     | T.EQ => signedCmp(I.CMPEQ,I.BNE)
1317 :     | T.NE => signedCmp(I.CMPEQ,I.BEQ)
1318 :     | T.LTU => unsignedCmp(ty,I.CMPULT,I.BNE)
1319 :     | T.LEU => unsignedCmp(ty,I.CMPULE,I.BNE)
1320 :     | T.GTU => unsignedCmp(ty,I.CMPULE,I.BEQ)
1321 :     | T.GEU => unsignedCmp(ty,I.CMPULT,I.BEQ)
1322 : leunga 744 | _ => error "branchItOther"
1323 : monnier 409 end
1324 :    
1325 :     (* This function generates a conditional move:
1326 :     * d = if cond(a,b) then x else y
1327 :     * Apparently, only signed comparisons conditional moves
1328 :     * are supported on the alpha.
1329 :     *)
1330 :     and cmove(ty,cond,a,b,x,y,d,an) =
1331 : george 545 let val tmp = newReg()
1332 :     val _ = doExpr(y,tmp,[]) (* evaluate false case *)
1333 : monnier 409
1334 :     val (cond,a,b) =
1335 :     (* move the immed operand to b *)
1336 :     case a of
1337 : george 761 (T.LI _ | T.CONST _) => (T.Basis.swapCond cond,b,a)
1338 : monnier 409 | _ => (cond,a,b)
1339 :    
1340 : george 761 fun sub(a, T.LI z) =
1341 :     if T.I.isZero z then expr a else expr(T.SUB(ty,a,b))
1342 :     | sub(a,b) = expr(T.SUB(ty,a,b))
1343 : monnier 409
1344 :     fun cmp(cond,e1,e2) =
1345 : george 545 let val flag = newReg()
1346 :     in compare(ty,cond,e1,e2,flag,[]); flag end
1347 : monnier 409
1348 :     val (oper,ra,x,y) =
1349 :     case (cond,isAndb1 a,zeroOrOne b) of
1350 :     (* low bit set/clear? *)
1351 :     (T.EQ,(true,e),ONE) => (I.CMOVLBS,expr e,x,y)
1352 :     | (T.EQ,(true,e),ZERO) => (I.CMOVLBC,expr e,x,y)
1353 :     | (T.NE,(true,e),ZERO) => (I.CMOVLBS,expr e,x,y)
1354 :     | (T.NE,(true,e),ONE) => (I.CMOVLBC,expr e,x,y)
1355 :     (* signed *)
1356 :     | (T.EQ,_,_) => (I.CMOVEQ,sub(a,b),x,y)
1357 :     | (T.NE,_,_) => (I.CMOVEQ,cmp(T.EQ,a,b),y,x)
1358 :     | (T.GT,_,_) => (I.CMOVGT,sub(a,b),x,y)
1359 :     | (T.GE,_,_) => (I.CMOVGE,sub(a,b),x,y)
1360 :     | (T.LT,_,_) => (I.CMOVLT,sub(a,b),x,y)
1361 :     | (T.LE,_,_) => (I.CMOVLE,sub(a,b),x,y)
1362 :    
1363 :     (* unsigned: do compare then use the condition code *)
1364 :     | (T.LTU,_,_) => (I.CMOVEQ,cmp(T.GEU,a,b),x,y)
1365 :     | (T.LEU,_,_) => (I.CMOVEQ,cmp(T.GTU,a,b),x,y)
1366 :     | (T.GTU,_,_) => (I.CMOVEQ,cmp(T.LEU,a,b),x,y)
1367 :     | (T.GEU,_,_) => (I.CMOVEQ,cmp(T.LTU,a,b),x,y)
1368 : leunga 744 | _ => error "cmove"
1369 : george 545 in mark(I.CMOVE{oper=oper,ra=ra,rb=opn x,rc=tmp},an); (* true case *)
1370 :     move(tmp, d, [])
1371 : monnier 409 end
1372 :    
1373 :    
1374 :     (* This function generates a comparion between e1 and e2 and writes
1375 :     * the result to register d.
1376 :     * It'll mask out the high order 32-bits when performing
1377 :     * unsigned 32-bit integer comparisons.
1378 :     *)
1379 :     and compare(ty,cond,e1,e2,d,an) =
1380 :     let fun signedCmp(oper,a,b,d) =
1381 :     mark(I.OPERATE{oper=oper,ra=expr a,rb=opn b,rc=d},an)
1382 :     fun unsignedCmp(ty,oper,a,b,d) =
1383 :     let val (x,y) = unsignedCmpOpnds(ty,a,b)
1384 :     in mark(I.OPERATE{oper=oper,ra=reduceOpn x,rb=y,rc=d},an)
1385 :     end
1386 :     fun eq(a,b,d) =
1387 :     (case (opn a,opn b) of
1388 :     (a,I.REGop r) =>
1389 :     mark(I.OPERATE{oper=I.CMPEQ,ra=r,rb=a,rc=d},an)
1390 :     | (a,b) =>
1391 :     mark(I.OPERATE{oper=I.CMPEQ,ra=reduceOpn a,rb=b,rc=d},an)
1392 :     )
1393 :     fun neq(a,b,d) =
1394 :     let val tmp = newReg()
1395 :     in eq(a,b,tmp);
1396 :     emit(I.OPERATE{oper=I.CMPEQ,ra=tmp,rb=zeroOpn,rc=d})
1397 :     end
1398 :     val (cond,e1,e2) =
1399 :     case e1 of
1400 : george 761 (T.LI _ | T.CONST _) =>
1401 : george 545 (T.Basis.swapCond cond,e2,e1)
1402 : monnier 409 | _ => (cond,e1,e2)
1403 :     in case cond of
1404 :     T.EQ => eq(e1,e2,d)
1405 :     | T.NE => neq(e1,e2,d)
1406 :     | T.GT => signedCmp(I.CMPLT,e2,e1,d)
1407 :     | T.GE => signedCmp(I.CMPLE,e2,e1,d)
1408 :     | T.LT => signedCmp(I.CMPLT,e1,e2,d)
1409 :     | T.LE => signedCmp(I.CMPLE,e1,e2,d)
1410 :     | T.GTU => unsignedCmp(ty,I.CMPULT,e2,e1,d)
1411 :     | T.GEU => unsignedCmp(ty,I.CMPULE,e2,e1,d)
1412 :     | T.LTU => unsignedCmp(ty,I.CMPULT,e1,e2,d)
1413 :     | T.LEU => unsignedCmp(ty,I.CMPULE,e1,e2,d)
1414 : leunga 744 | _ => error "compare"
1415 : monnier 409 end
1416 :    
1417 :     (* generate an unconditional branch *)
1418 : george 545 and goto(lab,an) = mark(I.BRANCH{b=I.BR,r=zeroR,lab=lab},an)
1419 : monnier 409
1420 :     (* generate an call instruction *)
1421 : leunga 624 and call(ea,flow,defs,uses,mem,an) =
1422 :     let val defs=cellset defs
1423 :     val uses=cellset uses
1424 :     val instr =
1425 :     case (ea, flow) of
1426 :     (T.LABEL(LE.LABEL lab), [_]) =>
1427 :     I.BSR{lab=lab,r=C.returnAddr,defs=defs,uses=uses,mem=mem}
1428 :     | _ => I.JSR{r=C.returnAddr,b=expr ea,
1429 :     d=0,defs=defs,uses=uses,mem=mem}
1430 :     in mark(instr,an)
1431 : monnier 409 end
1432 :    
1433 : george 545 and doCCexpr(T.CC(_,r),d,an) = move(r,d,an)
1434 :     | doCCexpr(T.FCC(_,r),d,an) = fmove(r,d,an)
1435 : monnier 409 | doCCexpr(T.CMP(ty,cond,e1,e2),d,an) = compare(ty,cond,e1,e2,d,an)
1436 :     | doCCexpr(T.FCMP(fty,cond,e1,e2),d,an) = error "doCCexpr"
1437 : george 545 | doCCexpr(T.CCMARK(e,A.MARKREG f),d,an) = (f d; doCCexpr(e,d,an))
1438 :     | doCCexpr(T.CCMARK(e,a),d,an) = doCCexpr(e,d,a::an)
1439 : george 555 | doCCexpr(T.CCEXT e,d,an) =
1440 :     ExtensionComp.compileCCext (reducer()) {e=e, ccd=d, an=an}
1441 : george 545 | doCCexpr _ = error "doCCexpr"
1442 : monnier 409
1443 : george 545 and ccExpr(T.CC(_,r)) = r
1444 :     | ccExpr(T.FCC(_,r)) = r
1445 : monnier 409 | ccExpr e = let val d = newReg()
1446 :     in doCCexpr(e,d,[]); d end
1447 :    
1448 :     (* compile a statement *)
1449 :     and stmt(s,an) =
1450 :     case s of
1451 :     T.MV(ty,r,e) => doExpr(e,r,an)
1452 :     | T.FMV(ty,r,e) => doFexpr(e,r,an)
1453 :     | T.CCMV(r,e) => doCCexpr(e,r,an)
1454 :     | T.COPY(ty,dst,src) => copy(dst,src,an)
1455 :     | T.FCOPY(ty,dst,src) => fcopy(dst,src,an)
1456 : leunga 744 | T.JMP(T.LABEL(LE.LABEL lab),_) => goto(lab,an)
1457 :     | T.JMP(e,labs) => mark(I.JMPL({r=zeroR,b=expr e,d=0},labs),an)
1458 :     | T.BCC(cc,lab) => branch(cc,lab,an)
1459 :     | T.CALL{funct,targets,defs,uses,region,...} =>
1460 : leunga 591 call(funct,targets,defs,uses,region,an)
1461 : leunga 628 | T.RET _ => mark(I.RET{r=zeroR,b=C.returnAddr,d=0},an)
1462 : monnier 409 | T.STORE(8,ea,data,mem) => store8(ea,data,mem,an)
1463 :     | T.STORE(16,ea,data,mem) => store16(ea,data,mem,an)
1464 :     | T.STORE(32,ea,data,mem) => store(I.STL,ea,data,mem,an)
1465 :     | T.STORE(64,ea,data,mem) => store(I.STQ,ea,data,mem,an)
1466 :     | T.FSTORE(32,ea,data,mem) => fstore(I.STS,ea,data,mem,an)
1467 :     | T.FSTORE(64,ea,data,mem) => fstore(I.STT,ea,data,mem,an)
1468 : george 545 | T.DEFINE l => defineLabel l
1469 : monnier 409 | T.ANNOTATION(s,a) => stmt(s,a::an)
1470 : george 555 | T.EXT s => ExtensionComp.compileSext (reducer()) {stm=s,an=an}
1471 : george 545 | s => doStmts (Gen.compileStm s)
1472 : monnier 409
1473 : george 545 and reducer() =
1474 :     T.REDUCER{reduceRexp = expr,
1475 :     reduceFexp = fexpr,
1476 :     reduceCCexp = ccExpr,
1477 :     reduceStm = stmt,
1478 :     operand = opn,
1479 :     reduceOperand = reduceOpn,
1480 :     addressOf = addr,
1481 :     emit = mark,
1482 :     instrStream = instrStream,
1483 :     mltreeStream = self()
1484 :     }
1485 :    
1486 : monnier 409 and doStmt s = stmt(s,[])
1487 : george 545 and doStmts ss = app doStmt ss
1488 : monnier 409
1489 : george 545 (* convert mlrisc to cellset:
1490 :     * condition code registers are mapped onto general registers
1491 :     *)
1492 :     and cellset mlrisc =
1493 :     let fun g([],acc) = acc
1494 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
1495 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
1496 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,C.addReg(cc,acc))
1497 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,C.addReg(cc,acc))
1498 :     | g(_::regs, acc) = g(regs, acc)
1499 :     in g(mlrisc, C.empty) end
1500 : monnier 409
1501 : george 545 and self() =
1502 :     S.STREAM
1503 :     { beginCluster= beginCluster,
1504 :     endCluster = endCluster,
1505 :     emit = doStmt,
1506 :     pseudoOp = pseudoOp,
1507 :     defineLabel = defineLabel,
1508 :     entryLabel = entryLabel,
1509 :     comment = comment,
1510 :     annotation = annotation,
1511 : leunga 744 exitBlock = fn regs => exitBlock(cellset regs)
1512 : george 545 }
1513 :     in self()
1514 : monnier 409 end
1515 :    
1516 :     end
1517 :    

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