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[smlnj] Annotation of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml
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Annotation of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml

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1 : monnier 409 (*
2 :     * This is a revamping of the Alpha32 instruction selection module
3 :     * using the new MLTREE and instruction representation. I've dropped
4 :     * the suffix 32 since we now support 64 bit datatypes.
5 :     *
6 :     * -- Allen
7 :     *
8 :     * Notes: places with optimizations are marked ***OPT***
9 :     *)
10 :    
11 :     functor Alpha
12 : leunga 744 (structure AlphaInstr : ALPHAINSTR
13 : monnier 409 structure PseudoInstrs : ALPHA_PSEUDO_INSTR
14 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
15 : leunga 775 where I = AlphaInstr
16 : monnier 475 sharing PseudoInstrs.I = AlphaInstr
17 : monnier 409
18 :     (* Cost of multiplication in cycles *)
19 :     val multCost : int ref
20 :    
21 :     (* Should we just use the native multiply by a constant? *)
22 :     val useMultByConst : bool ref
23 : george 545
24 :     (* Should we use SUD flags for floating point and generate DEFFREG?
25 :     * This should be set to false for C-like clients but true for SML/NJ.
26 :     *)
27 :     val SMLNJfloatingPoint : bool
28 : leunga 583
29 :     (* Should we use generate special byte/word load instructions
30 :     * like LDBU, LDWU, STB, STW.
31 :     *)
32 :     val byteWordLoadStores : bool ref
33 : monnier 409 ) : MLTREECOMP =
34 :     struct
35 :    
36 : leunga 775 structure I = AlphaInstr
37 :     structure C = I.C
38 :     structure T = I.T
39 : monnier 429 structure S = T.Stream
40 : leunga 775 structure R = T.Region
41 : monnier 409 structure W32 = Word32
42 : monnier 429 structure P = PseudoInstrs
43 : george 545 structure A = MLRiscAnnotations
44 : monnier 409
45 :     (*********************************************************
46 :    
47 :     Trap Shadows, Floating Exceptions, and Denormalized
48 :     Numbers on the DEC Alpha
49 :    
50 :     Andrew W. Appel and Lal George
51 :     Nov 28, 1995
52 :    
53 :     See section 4.7.5.1 of the Alpha Architecture Reference Manual.
54 :    
55 :     The Alpha has imprecise exceptions, meaning that if a floating
56 :     point instruction raises an IEEE exception, the exception may
57 :     not interrupt the processor until several successive instructions have
58 :     completed. ML, on the other hand, may want a "precise" model
59 :     of floating point exceptions.
60 :    
61 :     Furthermore, the Alpha hardware does not support denormalized numbers
62 :     (for "gradual underflow"). Instead, underflow always rounds to zero.
63 :     However, each floating operation (add, mult, etc.) has a trapping
64 :     variant that will raise an exception (imprecisely, of course) on
65 :     underflow; in that case, the instruction will produce a zero result
66 :     AND an exception will occur. In fact, there are several variants
67 :     of each instruction; three variants of MULT are:
68 :    
69 :     MULT s1,s2,d truncate denormalized result to zero; no exception
70 :     MULT/U s1,s2,d truncate denormalized result to zero; raise UNDERFLOW
71 :     MULT/SU s1,s2,d software completion, producing denormalized result
72 :    
73 :     The hardware treats the MULT/U and MULT/SU instructions identically,
74 :     truncating a denormalized result to zero and raising the UNDERFLOW
75 :     exception. But the operating system, on an UNDERFLOW exception,
76 :     examines the faulting instruction to see if it's an /SU form, and if so,
77 :     recalculates s1*s2, puts the right answer in d, and continues,
78 :     all without invoking the user's signal handler.
79 :    
80 :     Because most machines compute with denormalized numbers in hardware,
81 :     to maximize portability of SML programs, we use the MULT/SU form.
82 :     (and ADD/SU, SUB/SU, etc.) But to use this form successfully,
83 :     certain rules have to be followed. Basically, d cannot be the same
84 :     register as s1 or s2, because the opsys needs to be able to
85 :     recalculate the operation using the original contents of s1 and s2,
86 :     and the MULT/SU instruction will overwrite d even if it traps.
87 :    
88 :     More generally, we may want to have a sequence of floating-point
89 :     instructions. The rules for such a sequence are:
90 :    
91 :     1. The sequence should end with a TRAPB (trap barrier) instruction.
92 :     (This could be relaxed somewhat, but certainly a TRAPB would
93 :     be a good idea sometime before the next branch instruction or
94 :     update of an ML reference variable, or any other ML side effect.)
95 :     2. No instruction in the sequence should destroy any operand of itself
96 :     or of any previous instruction in the sequence.
97 :     3. No two instructions in the sequence should write the same destination
98 :     register.
99 :    
100 :     We can achieve these conditions by the following trick in the
101 :     Alpha code generator. Each instruction in the sequence will write
102 :     to a different temporary; this is guaranteed by the translation from
103 :     ML-RISC. At the beginning of the sequence, we will put a special
104 :     pseudo-instruction (we call it DEFFREG) that "defines" the destination
105 :     register of the arithmetic instruction. If there are K arithmetic
106 :     instructions in the sequence, then we'll insert K DEFFREG instructions
107 :     all at the beginning of the sequence.
108 :     Then, each arithop will not only "define" its destination temporary
109 :     but will "use" it as well. When all these instructions are fed to
110 :     the liveness analyzer, the resulting interference graph will then
111 :     have inteference edges satisfying conditions 2 and 3 above.
112 :    
113 :     Of course, DEFFREG doesn't actually generate any code. In our model
114 :     of the Alpha, every instruction generates exactly 4 bytes of code
115 :     except the "span-dependent" ones. Therefore, we'll specify DEFFREG
116 :     as a span-dependent instruction whose minimum and maximum sizes are zero.
117 :    
118 :     At the moment, we do not group arithmetic operations into sequences;
119 :     that is, each arithop will be preceded by a single DEFFREG and
120 :     followed by a TRAPB. To avoid the cost of all those TRAPB's, we
121 :     should improve this when we have time. Warning: Don't put more
122 :     than 31 instructions in the sequence, because they're all required
123 :     to write to different destination registers!
124 :    
125 :     What about multiple traps? For example, suppose a sequence of
126 :     instructions produces an Overflow and a Divide-by-Zero exception?
127 :     ML would like to know only about the earliest trap, but the hardware
128 :     will report BOTH traps to the operating system. However, as long
129 :     as the rules above are followed (and the software-completion versions
130 :     of the arithmetic instructions are used), the operating system will
131 :     have enough information to know which instruction produced the
132 :     trap. It is very probable that the operating system will report ONLY
133 :     the earlier trap to the user process, but I'm not sure.
134 :    
135 :     For a hint about what the operating system is doing in its own
136 :     trap-handler (with software completion), see section 6.3.2 of
137 :     "OpenVMS Alpha Software" (Part II of the Alpha Architecture
138 :     Manual). This stuff should apply to Unix (OSF1) as well as VMS.
139 :    
140 :     ****************************************************************)
141 :    
142 :     fun error msg = MLRiscErrorMsg.error("Alpha",msg)
143 :    
144 : leunga 744 type instrStream = (I.instruction,C.cellset) T.stream
145 :     type mltreeStream = (T.stm,T.mlrisc list) T.stream
146 : monnier 409
147 :     (*
148 :     * This module is used to simulate operations of non-standard widths.
149 :     *)
150 :     structure Gen = MLTreeGen(structure T = T
151 :     val intTy = 64
152 :     val naturalWidths = [32,64]
153 : monnier 429 datatype rep = SE | ZE | NEITHER
154 :     val rep = SE
155 : monnier 409 )
156 :    
157 : leunga 744 val zeroR = C.r31
158 : monnier 409 val zeroOpn = I.REGop zeroR
159 : george 761 fun LI i = T.LI(T.I.fromInt(32, i))
160 :     fun toInt i = T.I.toInt(32, i)
161 :     val int_0 = T.I.int_0
162 :     val int_1 = T.I.int_1
163 : leunga 775 fun EQ(x:IntInf.int,y) = x=y
164 : monnier 409
165 :     (*
166 :     * Specialize the modules for multiplication/division
167 :     * by constant optimizations.
168 :     *)
169 :     functor Multiply32 = MLTreeMult
170 :     (structure I = I
171 :     structure T = T
172 :    
173 :     val intTy = 32
174 :    
175 : monnier 429 type arg = {r1:C.cell,r2:C.cell,d:C.cell}
176 :     type argi = {r:C.cell,i:int,d:C.cell}
177 : monnier 409
178 :     fun mov{r,d} = I.COPY{dst=[d],src=[r],tmp=NONE,impl=ref NONE}
179 :     fun add{r1,r2,d} = I.OPERATE{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}
180 :     (*
181 :     * How to left shift by a constant (32bits)
182 :     *)
183 :     fun slli{r,i=1,d} = [I.OPERATE{oper=I.ADDL,ra=r,rb=I.REGop r,rc=d}]
184 :     | slli{r,i=2,d} = [I.OPERATE{oper=I.S4ADDL,ra=r,rb=zeroOpn,rc=d}]
185 :     | slli{r,i=3,d} = [I.OPERATE{oper=I.S8ADDL,ra=r,rb=zeroOpn,rc=d}]
186 :     | slli{r,i,d} =
187 :     let val tmp = C.newReg()
188 :     in [I.OPERATE{oper=I.SLL,ra=r,rb=I.IMMop i,rc=tmp},
189 : leunga 646 I.OPERATE{oper=I.ADDL,ra=tmp,rb=zeroOpn,rc=d}]
190 : monnier 409 end
191 :    
192 :     (*
193 :     * How to right shift (unsigned) by a constant (32bits)
194 :     *)
195 :     fun srli{r,i,d} =
196 :     let val tmp = C.newReg()
197 :     in [I.OPERATE{oper=I.ZAP,ra=r,rb=I.IMMop 0xf0,rc=tmp},
198 :     I.OPERATE{oper=I.SRL,ra=tmp,rb=I.IMMop i,rc=d}]
199 :     end
200 :    
201 :     (*
202 :     * How to right shift (signed) by a constant (32bits)
203 :     *)
204 :     fun srai{r,i,d} =
205 :     let val tmp = C.newReg()
206 : leunga 646 in [I.OPERATE{oper=I.ADDL,ra=r,rb=zeroOpn,rc=tmp},
207 : monnier 409 I.OPERATE{oper=I.SRA,ra=tmp,rb=I.IMMop i,rc=d}]
208 :     end
209 :     )
210 :    
211 :     functor Multiply64 = MLTreeMult
212 :     (structure I = I
213 :     structure T = T
214 :    
215 :     val intTy = 64
216 :    
217 : monnier 429 type arg = {r1:C.cell,r2:C.cell,d:C.cell}
218 :     type argi = {r:C.cell,i:int,d:C.cell}
219 : monnier 409
220 :     fun mov{r,d} = I.COPY{dst=[d],src=[r],tmp=NONE,impl=ref NONE}
221 :     fun add{r1,r2,d}= I.OPERATE{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}
222 :     fun slli{r,i,d} = [I.OPERATE{oper=I.SLL,ra=r,rb=I.IMMop i,rc=d}]
223 :     fun srli{r,i,d} = [I.OPERATE{oper=I.SRL,ra=r,rb=I.IMMop i,rc=d}]
224 :     fun srai{r,i,d} = [I.OPERATE{oper=I.SRA,ra=r,rb=I.IMMop i,rc=d}]
225 :     )
226 :    
227 :     (* signed, trapping version of multiply and divide *)
228 :     structure Mult32 = Multiply32
229 :     (val trapping = true
230 :     val multCost = multCost
231 :     fun addv{r1,r2,d} = [I.OPERATEV{oper=I.ADDLV,ra=r1,rb=I.REGop r2,rc=d}]
232 :     fun subv{r1,r2,d} = [I.OPERATEV{oper=I.SUBLV,ra=r1,rb=I.REGop r2,rc=d}]
233 :     val sh1addv = NONE
234 :     val sh2addv = NONE
235 :     val sh3addv = NONE
236 :     )
237 : monnier 429 (val signed = true)
238 : monnier 409
239 : monnier 429 (* non-trapping version of multiply and divide *)
240 :     functor Mul32 = Multiply32
241 : monnier 409 (val trapping = false
242 :     val multCost = multCost
243 :     fun addv{r1,r2,d} = [I.OPERATE{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}]
244 :     fun subv{r1,r2,d} = [I.OPERATE{oper=I.SUBL,ra=r1,rb=I.REGop r2,rc=d}]
245 :     val sh1addv = NONE
246 :     val sh2addv = SOME(fn {r1,r2,d} =>
247 :     [I.OPERATE{oper=I.S4ADDL,ra=r1,rb=I.REGop r2,rc=d}])
248 :     val sh3addv = SOME(fn {r1,r2,d} =>
249 :     [I.OPERATE{oper=I.S8ADDL,ra=r1,rb=I.REGop r2,rc=d}])
250 :     )
251 : monnier 429 structure Mulu32 = Mul32(val signed = false)
252 :     structure Muls32 = Mul32(val signed = true)
253 : monnier 409
254 :     (* signed, trapping version of multiply and divide *)
255 :     structure Mult64 = Multiply64
256 :     (val trapping = true
257 :     val multCost = multCost
258 :     fun addv{r1,r2,d} = [I.OPERATEV{oper=I.ADDQV,ra=r1,rb=I.REGop r2,rc=d}]
259 :     fun subv{r1,r2,d} = [I.OPERATEV{oper=I.SUBQV,ra=r1,rb=I.REGop r2,rc=d}]
260 :     val sh1addv = NONE
261 :     val sh2addv = NONE
262 :     val sh3addv = NONE
263 :     )
264 : monnier 429 (val signed = true)
265 : monnier 409
266 :     (* unsigned, non-trapping version of multiply and divide *)
267 : monnier 429 functor Mul64 = Multiply64
268 : monnier 409 (val trapping = false
269 :     val multCost = multCost
270 :     fun addv{r1,r2,d} = [I.OPERATE{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}]
271 :     fun subv{r1,r2,d} = [I.OPERATE{oper=I.SUBQ,ra=r1,rb=I.REGop r2,rc=d}]
272 :     val sh1addv = NONE
273 :     val sh2addv = SOME(fn {r1,r2,d} =>
274 :     [I.OPERATE{oper=I.S4ADDQ,ra=r1,rb=I.REGop r2,rc=d}])
275 :     val sh3addv = SOME(fn {r1,r2,d} =>
276 :     [I.OPERATE{oper=I.S8ADDQ,ra=r1,rb=I.REGop r2,rc=d}])
277 :     )
278 : monnier 429 structure Mulu64 = Mul64(val signed = false)
279 :     structure Muls64 = Mul64(val signed = true)
280 : monnier 409
281 :     (*
282 :     * The main stuff
283 :     *)
284 :    
285 : george 761 datatype times4or8 = TIMES1 | TIMES4 | TIMES8
286 : monnier 409 datatype zeroOne = ZERO | ONE | OTHER
287 :     datatype commutative = COMMUTE | NOCOMMUTE
288 :    
289 : leunga 744 val zeroFR = C.f31
290 : leunga 583 val zeroEA = I.Direct zeroR
291 : george 761 val zeroT = T.LI int_0
292 : leunga 583 val trapb = [I.TRAPB]
293 :     val zeroImm = I.IMMop 0
294 :    
295 : monnier 409 fun selectInstructions
296 : george 545 (instrStream as
297 : leunga 815 S.STREAM{emit,beginCluster,endCluster,getAnnotations,
298 : monnier 429 defineLabel,entryLabel,pseudoOp,annotation,
299 : leunga 744 exitBlock,comment,...}) =
300 : monnier 409 let
301 :     infix || && << >> ~>>
302 :    
303 :     val op || = W32.orb
304 :     val op && = W32.andb
305 :     val op << = W32.<<
306 :     val op >> = W32.>>
307 :     val op ~>> = W32.~>>
308 :    
309 :     val itow = Word.fromInt
310 :     val wtoi = Word.toIntX
311 :    
312 :     val newReg = C.newReg
313 :     val newFreg = C.newFreg
314 :    
315 :     (* Choose the appropriate rounding mode to generate.
316 :     * This stuff is used to support the alpha32x SML/NJ backend.
317 : monnier 429 *
318 :     *
319 :     * Floating point rounding mode.
320 :     * When this is set to true, we use the /SU rounding mode
321 :     * (chopped towards zero) for floating point arithmetic.
322 :     * This flag is only used to support the old alpha32x backend.
323 :     *
324 :     * Otherwise, we use /SUD. This is the default for SML/NJ.
325 :     *
326 : monnier 409 *)
327 : george 545 val (ADDTX,SUBTX,MULTX,DIVTX) =
328 :     (I.ADDTSUD,I.SUBTSUD,I.MULTSUD,I.DIVTSUD)
329 :     val (ADDSX,SUBSX,MULSX,DIVSX) =
330 :     (I.ADDSSUD,I.SUBSSUD,I.MULSSUD,I.DIVSSUD)
331 : monnier 409
332 :     fun mark'(i,[]) = i
333 :     | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
334 :     fun mark(i,an) = emit(mark'(i,an))
335 :    
336 :     (* Fit within 16 bits? *)
337 :     fun literal16 n = ~32768 <= n andalso n < 32768
338 :     fun literal16w w =
339 :     let val hi = W32.~>>(w,0wx16)
340 :     in hi = 0w0 orelse (W32.notb hi) = 0w0 end
341 :    
342 :     (* emit an LDA instruction; return the register that holds the value *)
343 :     fun lda(base,I.IMMop 0) = base
344 :     | lda(base,offset) =
345 :     let val r = newReg()
346 :     in emit(I.LDA{r=r, b=base, d=offset}); r end
347 :    
348 :     (* emit load immed *)
349 : george 761 fun loadImmed(n, base, rd, an) = let
350 :     val n = T.I.toInt32(32, n)
351 :     in
352 :     if n = 0 then move(base, rd, an)
353 :     else if ~32768 <= n andalso n < 32768 then
354 :     mark(I.LDA{r=rd, b=base, d=I.IMMop(Int32.toInt n)}, an)
355 :     else loadImmed32(n, base, rd, an)
356 : monnier 409 end
357 :    
358 :     (* loadImmed32 is used to load int32 and word32 constants.
359 :     * In either case we sign extend the 32-bit value. This is compatible
360 :     * with LDL which sign extends a 32-bit valued memory location.
361 :     *)
362 : george 761 (* TODO:
363 :     * Should handle 64 bits if immediate is not in the 32 bit range.
364 :     *)
365 :     and loadImmed32(n, base, rd, an) = let
366 :     fun immed(0, high) =
367 :     mark(I.LDAH{r=rd, b=base, d=I.IMMop(high)}, an)
368 :     | immed(low, 0) =
369 :     mark(I.LDA{r=rd, b=base, d=I.IMMop(low)}, an)
370 :     | immed(low, high) =
371 :     (emit(I.LDA{r=rd, b=base, d=I.IMMop(low)});
372 :     mark(I.LDAH{r=rd, b=rd, d=I.IMMop(high)}, an)
373 :     )
374 :     val w = Word32.fromLargeInt(Int32.toLarge n)
375 :     val low = W32.andb(w, 0wxffff)
376 :     val high = W32.~>>(w, 0w16)
377 :     in
378 :     if W32.<(low, 0wx8000) then
379 :     immed(W32.toInt low, W32.toIntX high)
380 :     else let
381 :     val low = W32.toIntX(W32.-(low, 0wx10000))
382 :     val high = W32.toIntX(W32.+(high, 0w1))
383 : monnier 409 in
384 : george 761 if high <> 0x8000 then immed(low, high)
385 :     else let (* transition of high from pos to neg *)
386 :     val tmpR1 = newReg()
387 :     val tmpR2 = newReg()
388 :     val tmpR3=newReg()
389 :     in
390 :     (* you just gotta do, what you gotta do! *)
391 :     emit(I.LDA{r=tmpR3, b=base, d=I.IMMop(low)});
392 :     emit(I.OPERATE{oper=I.ADDQ, ra=zeroR, rb=I.IMMop 1, rc=tmpR1});
393 :     emit(I.OPERATE{oper=I.SLL, ra=tmpR1, rb=I.IMMop 31, rc=tmpR2});
394 :     mark(I.OPERATE{oper=I.ADDQ, ra=tmpR2, rb=I.REGop tmpR3, rc=rd},an)
395 :     end
396 :     end
397 :     end
398 : monnier 409
399 : george 761
400 : leunga 775 (* emit load label expression *)
401 :     and loadLabexp(le,d,an) = mark(I.LDA{r=d,b=zeroR,d=I.LABop le},an)
402 : monnier 409
403 :     (* emit a copy *)
404 : monnier 469 and copy(dst,src,an) =
405 : monnier 409 mark(I.COPY{dst=dst,src=src,impl=ref NONE,
406 :     tmp=case dst of
407 :     [_] => NONE | _ => SOME(I.Direct(newReg()))},an)
408 :    
409 :     (* emit a floating point copy *)
410 : monnier 469 and fcopy(dst,src,an) =
411 : monnier 409 mark(I.FCOPY{dst=dst,src=src,impl=ref NONE,
412 :     tmp=case dst of
413 :     [_] => NONE | _ => SOME(I.FDirect(newFreg()))},an)
414 :    
415 : monnier 469 and move(s,d,an) =
416 : leunga 744 if C.sameCell(s,d) orelse C.sameCell(d,zeroR) then () else
417 : monnier 409 mark(I.COPY{dst=[d],src=[s],impl=ref NONE,tmp=NONE},an)
418 :    
419 : monnier 469 and fmove(s,d,an) =
420 : leunga 744 if C.sameCell(s,d) orelse C.sameCell(d,zeroFR) then () else
421 : monnier 409 mark(I.FCOPY{dst=[d],src=[s],impl=ref NONE,tmp=NONE},an)
422 :    
423 :     (* emit an sign extension op *)
424 : monnier 469 and signExt32(r,d) =
425 : leunga 646 emit(I.OPERATE{oper=I.ADDL,ra=r,rb=zeroOpn,rc=d})
426 : monnier 409
427 :     (* emit an commutative arithmetic op *)
428 : monnier 469 and commArith(opcode,a,b,d,an) =
429 : monnier 409 case (opn a,opn b) of
430 :     (I.REGop r,i) => mark(I.OPERATE{oper=opcode,ra=r,rb=i,rc=d},an)
431 :     | (i,I.REGop r) => mark(I.OPERATE{oper=opcode,ra=r,rb=i,rc=d},an)
432 :     | (r,i) => mark(I.OPERATE{oper=opcode,ra=reduceOpn r,rb=i,rc=d},an)
433 :    
434 :     (* emit an arithmetic op *)
435 :     and arith(opcode,a,b,d,an) =
436 :     mark(I.OPERATE{oper=opcode,ra=expr a,rb=opn b,rc=d},an)
437 :     and arith'(opcode,a,b,d,an) =
438 :     let val rb = opn b
439 :     val ra = expr a
440 :     in mark(I.OPERATE{oper=opcode,ra=ra,rb=rb,rc=d},an) end
441 :    
442 :     (* emit a trapping commutative arithmetic op *)
443 :     and commArithTrap(opcode,a,b,d,an) =
444 :     (case (opn a,opn b) of
445 :     (I.REGop r,i) => mark(I.OPERATEV{oper=opcode,ra=r,rb=i,rc=d},an)
446 :     | (i,I.REGop r) => mark(I.OPERATEV{oper=opcode,ra=r,rb=i,rc=d},an)
447 :     | (r,i) => mark(I.OPERATEV{oper=opcode,ra=reduceOpn r,rb=i,rc=d},an);
448 :     emit(I.TRAPB)
449 :     )
450 :    
451 :     (* emit a trapping arithmetic op *)
452 :     and arithTrap(opcode,a,b,d,an) =
453 :     (mark(I.OPERATEV{oper=opcode,ra=expr a,rb=opn b,rc=d},an);
454 :     emit(I.TRAPB)
455 :     )
456 :    
457 :     (* convert an operand into a register *)
458 :     and reduceOpn(I.REGop r) = r
459 :     | reduceOpn(I.IMMop 0) = zeroR
460 :     | reduceOpn opn =
461 :     let val d = newReg()
462 :     in emit(I.OPERATE{oper=I.BIS,ra=zeroR,rb=opn,rc=d}); d end
463 :    
464 :     (* convert an expression into an operand *)
465 :     and opn(T.REG(_,r)) = I.REGop r
466 :     | opn(e as T.LI n) =
467 : leunga 775 if IntInf.<=(n, T.I.int_0xff) andalso IntInf.>=(n, T.I.int_0) then
468 : george 761 I.IMMop(toInt(n))
469 : monnier 409 else let val tmpR = newReg()
470 :     in loadImmed(n,zeroR,tmpR,[]); I.REGop tmpR end
471 : leunga 815 | opn(e as T.CONST _) = I.LABop e
472 : leunga 775 | opn(T.LABEXP x) = I.LABop x
473 : monnier 409 | opn e = I.REGop(expr e)
474 :    
475 : leunga 583 (* compute base+displacement from an expression
476 :     *)
477 : monnier 409 and addr exp =
478 : leunga 775 let fun toLexp(I.IMMop i) = T.LI(IntInf.fromInt i)
479 : leunga 583 | toLexp(I.LABop le) = le
480 :     | toLexp _ = error "addr.toLexp"
481 : monnier 409
482 : leunga 775 fun add(t,n,I.IMMop m) =
483 :     I.IMMop(toInt(T.I.ADD(t,n,IntInf.fromInt m)))
484 :     | add(t,n,I.LABop le) = I.LABop(T.ADD(t,T.LI n,le))
485 :     | add(t,n,_) = error "addr.add"
486 :    
487 :     fun addLe(ty,le,I.IMMop 0) = I.LABop le
488 :     | addLe(ty,le,disp) = I.LABop(T.ADD(ty,le,toLexp disp))
489 :    
490 :     fun sub(t,n,I.IMMop m) =
491 :     I.IMMop(toInt(T.I.SUB(t,IntInf.fromInt m,n)))
492 :     | sub(t,n,I.LABop le) = I.LABop(T.SUB(t,le,T.LI n))
493 :     | sub(t,n,_) = error "addr.sub"
494 :    
495 :     fun subLe(ty,le,I.IMMop 0) = I.LABop le
496 :     | subLe(ty,le,disp) = I.LABop(T.SUB(ty,le,toLexp disp))
497 : leunga 583
498 :     (* Should really take into account of the address width XXX *)
499 : leunga 775 fun fold(T.ADD(t,e,T.LI n),disp) = fold(e,add(t,n,disp))
500 :     | fold(T.ADD(t,e,x as T.CONST _),disp) = fold(e,addLe(t,x,disp))
501 :     | fold(T.ADD(t,e,x as T.LABEL _),disp) = fold(e,addLe(t,x,disp))
502 :     | fold(T.ADD(t,e,T.LABEXP l),disp) = fold(e,addLe(t,l,disp))
503 :     | fold(T.ADD(t,T.LI n,e),disp) = fold(e, add(t,n,disp))
504 :     | fold(T.ADD(t,x as T.CONST _,e),disp) = fold(e,addLe(t,x,disp))
505 :     | fold(T.ADD(t,x as T.LABEL _,e),disp) = fold(e,addLe(t,x,disp))
506 :     | fold(T.ADD(t,T.LABEXP l,e),disp) = fold(e,addLe(t,l,disp))
507 :     | fold(T.SUB(t,e,T.LI n),disp) = fold(e,sub(t,n,disp))
508 :     | fold(T.SUB(t,e,x as T.CONST _),disp) = fold(e,subLe(t,x,disp))
509 :     | fold(T.SUB(t,e,x as T.LABEL _),disp) = fold(e,subLe(t,x,disp))
510 :     | fold(T.SUB(t,e,T.LABEXP l),disp) = fold(e,subLe(t,l,disp))
511 : leunga 583 | fold(e,disp) = (expr e,disp)
512 :    
513 :     in makeEA(fold(exp, zeroImm))
514 :     end
515 :    
516 : monnier 409 (* compute base+displacement+small offset *)
517 :     and offset(base,disp as I.IMMop n,off) =
518 :     let val n' = n+off
519 :     in if literal16 n' then (base,I.IMMop n')
520 :     else
521 :     let val tmp = newReg()
522 :     in emit(I.OPERATE{oper=I.ADDQ,ra=base,rb=disp,rc=tmp});
523 :     (tmp,I.IMMop off)
524 :     end
525 :     end
526 : leunga 583 | offset(base,disp as I.LABop le,off) =
527 : leunga 775 (base, I.LABop(T.ADD(64,le,T.LI(IntInf.fromInt off))))
528 : monnier 409 | offset(base,disp,off) =
529 :     let val tmp = newReg()
530 :     in emit(I.OPERATE{oper=I.ADDQ,ra=base,rb=disp,rc=tmp});
531 :     (tmp,I.IMMop off)
532 :     end
533 :    
534 : leunga 583 (* check if base offset fits within the field *)
535 :     and makeEA(base, off as I.IMMop offset) =
536 :     if ~32768 <= offset andalso offset <= 32767
537 :     then (base, off)
538 : monnier 409 else
539 :     let val tmpR = newReg()
540 :     (* unsigned low 16 bits *)
541 :     val low = wtoi(Word.andb(itow offset, 0wxffff))
542 :     val high = offset div 65536
543 :     val (lowsgn, highsgn) = (* Sign-extend *)
544 :     if low <= 32767 then (low, high) else (low -65536, high+1)
545 :     in
546 :     (emit(I.LDAH{r=tmpR, b=base, d=I.IMMop highsgn});
547 :     (tmpR, I.IMMop lowsgn))
548 :     end
549 : leunga 583 | makeEA(base, offset) = (base, offset)
550 : monnier 409
551 :     (* look for multiply by 4 and 8 of the given type *)
552 :     and times4or8(ty,e) =
553 : george 761 let
554 :     fun f(t,a,n) = if t = ty then
555 :     if EQ(n, T.I.int_4) then (TIMES4,a)
556 :     else if EQ(n, T.I.int_8) then (TIMES8,a)
557 : monnier 409 else (TIMES1,e)
558 :     else (TIMES1,e)
559 : george 761
560 : monnier 409 fun u(t,a,n) = if t = ty then
561 : george 761 if EQ(n, T.I.int_2) then (TIMES4,a)
562 :     else if EQ(n, T.I.int_3) then (TIMES8,a)
563 : monnier 409 else (TIMES1,e)
564 :     else (TIMES1,e)
565 :     in case e of
566 :     T.MULU(t,a,T.LI n) => f(t,a,n)
567 :     | T.MULS(t,T.LI n,a) => f(t,a,n)
568 :     | T.SLL(t,a,T.LI n) => u(t,a,n)
569 :     | _ => (TIMES1,e)
570 :     end
571 :    
572 :     (* generate an add instruction
573 :     * ***OPT*** look for multiply by 4 and 8 and use the S4ADD and S8ADD
574 :     * forms.
575 :     *)
576 :     and plus(ty,add,s4add,s8add,a,b,d,an) =
577 :     (case times4or8(ty,a) of
578 :     (TIMES4,a) => arith(s4add,a,b,d,an)
579 :     | (TIMES8,a) => arith(s8add,a,b,d,an)
580 :     | _ =>
581 :     case times4or8(ty,b) of
582 :     (TIMES4,b) => arith'(s4add,b,a,d,an)
583 :     | (TIMES8,b) => arith'(s8add,b,a,d,an)
584 :     | _ => commArith(add,a,b,d,an)
585 :     )
586 :    
587 :     (* generate a subtract instruction
588 :     * ***OPT*** look for multiply by 4 and 8
589 :     *)
590 :     and minus(ty,sub,s4sub,s8sub,a,b,d,an) =
591 :     (case times4or8(ty,a) of
592 :     (TIMES4,a) => arith(s4sub,a,b,d,an)
593 :     | (TIMES8,a) => arith(s8sub,a,b,d,an)
594 :     | _ =>
595 : monnier 429 if ty = 64 then
596 : monnier 409 (case b of
597 :     (* use LDA to handle subtraction when possible
598 :     * Note: this may have sign extension problems later.
599 :     *)
600 : george 761 T.LI i => (loadImmed(T.I.NEGT(32,i),expr a,d,an) handle _ =>
601 : monnier 409 arith(sub,a,b,d,an))
602 :     | _ => arith(sub,a,b,d,an)
603 : monnier 429 ) else arith(sub,a,b,d,an)
604 : monnier 409 )
605 :    
606 :     (* look for special constants *)
607 : george 761 and wordOpn(T.LI n) = SOME(T.I.toWord32(32, n))
608 : monnier 409 | wordOpn e = NONE
609 :    
610 : monnier 429 (* look for special byte mask constants
611 :     * IMPORTANT: we must ALWAYS keep the sign bit!
612 :     *)
613 :     and byteMask(_,SOME 0wx00000000) = 0xff
614 :     | byteMask(_,SOME 0wx000000ff) = 0xfe
615 :     | byteMask(_,SOME 0wx0000ff00) = 0xfd
616 :     | byteMask(_,SOME 0wx0000ffff) = 0xfc
617 :     | byteMask(_,SOME 0wx00ff0000) = 0xfb
618 :     | byteMask(_,SOME 0wx00ff00ff) = 0xfa
619 :     | byteMask(_,SOME 0wx00ffff00) = 0xf9
620 :     | byteMask(_,SOME 0wx00ffffff) = 0xf8
621 :     | byteMask(ty,SOME 0wxff000000) = if ty = 64 then 0xf7 else 0x07
622 :     | byteMask(ty,SOME 0wxff0000ff) = if ty = 64 then 0xf6 else 0x06
623 :     | byteMask(ty,SOME 0wxff00ff00) = if ty = 64 then 0xf5 else 0x05
624 :     | byteMask(ty,SOME 0wxff00ffff) = if ty = 64 then 0xf4 else 0x04
625 :     | byteMask(ty,SOME 0wxffff0000) = if ty = 64 then 0xf3 else 0x03
626 :     | byteMask(ty,SOME 0wxffff00ff) = if ty = 64 then 0xf2 else 0x02
627 :     | byteMask(ty,SOME 0wxffffff00) = if ty = 64 then 0xf1 else 0x01
628 :     | byteMask(ty,SOME 0wxffffffff) = if ty = 64 then 0xf0 else 0x00
629 :     | byteMask _ = ~1
630 : monnier 409
631 :     (* generate an and instruction
632 :     * look for special masks.
633 :     *)
634 :     and andb(ty,a,b,d,an) =
635 :     case byteMask(ty,wordOpn a) of
636 : monnier 429 ~1 => (case byteMask(ty,wordOpn b) of
637 :     ~1 => commArith(I.AND,a,b,d,an)
638 : george 761 | mask => arith(I.ZAP,a,LI mask,d,an)
639 : monnier 429 )
640 : george 761 | mask => arith(I.ZAP,b,LI mask,d,an)
641 : monnier 409
642 :     (* generate sll/sra/srl *)
643 :     and sll32(a,b,d,an) =
644 :     case wordOpn b of
645 :     SOME 0w0 => doExpr(a,d,an)
646 :     | SOME 0w1 =>
647 :     let val r = T.REG(32,expr a) in arith(I.ADDL,r,r,d,an) end
648 :     | SOME 0w2 => arith(I.S4ADDL,a,zeroT,d,an)
649 :     | SOME 0w3 => arith(I.S8ADDL,a,zeroT,d,an)
650 :     | _ => let val t = newReg()
651 :     in arith(I.SLL,a,b,t,an);
652 :     signExt32(t,d)
653 :     end
654 :    
655 :     and sll64(a,b,d,an) =
656 :     case wordOpn b of
657 :     SOME 0w0 => doExpr(a,d,an)
658 :     | SOME 0w1 =>
659 :     let val r = T.REG(64,expr a) in arith(I.ADDQ,r,r,d,an) end
660 :     | SOME 0w2 => arith(I.S4ADDQ,a,zeroT,d,an)
661 :     | SOME 0w3 => arith(I.S8ADDQ,a,zeroT,d,an)
662 :     | _ => arith(I.SLL,a,b,d,an)
663 :    
664 : leunga 796 (* On the alpha, all 32 bit values are already sign extended.
665 :     * So no sign extension is necessary. We do the same for
666 :     * sra32 and sra64
667 :     *)
668 :     and sra(a,b,d,an) =
669 : monnier 409 mark(I.OPERATE{oper=I.SRA,ra=expr a,rb=opn b,rc=d},an)
670 :    
671 :     and srl32(a,b,d,an) =
672 :     let val ra = expr a
673 :     val rb = opn b
674 :     val t = newReg()
675 :     in emit(I.OPERATE{oper=I.ZAP,ra=ra,rb=I.IMMop 0xf0,rc=t});
676 :     mark(I.OPERATE{oper=I.SRL,ra=t,rb=rb,rc=d},an)
677 :     end
678 :    
679 :     and srl64(a,b,d,an) =
680 :     mark(I.OPERATE{oper=I.SRL,ra=expr a,rb=opn b,rc=d},an)
681 :    
682 :     (*
683 :     * Generic multiply.
684 :     * We first try to use the multiply by constant heuristic
685 :     *)
686 :     and multiply(ty,gen,genConst,e1,e2,rd,trapb,an) =
687 :     let fun nonconst(e1,e2) =
688 :     let val instr =
689 :     case (opn e1,opn e2) of
690 :     (i,I.REGop r) => gen{ra=r,rb=i,rc=rd}
691 :     | (I.REGop r,i) => gen{ra=r,rb=i,rc=rd}
692 :     | (r,i) => gen{ra=reduceOpn r,rb=i,rc=rd}
693 :     in mark'(instr,an)::trapb end
694 :     fun const(e,i) =
695 :     let val r = expr e
696 : george 761 in if !useMultByConst andalso
697 : leunga 775 IntInf.>=(i, T.I.int_0) andalso
698 :     IntInf.<(i, T.I.int_0x100) then
699 : george 761 mark'(gen{ra=r,rb=I.IMMop(toInt i),rc=rd},an)::trapb
700 : monnier 409 else
701 : george 761 (genConst{r=r,i=toInt i,d=rd}@trapb
702 : monnier 409 handle _ => nonconst(T.REG(ty,r),T.LI i))
703 :     end
704 :     val instrs =
705 : george 761 case (e1, e2)
706 :     of (_, T.LI i) => const(e1, i)
707 :     | (T.LI i, _) => const(e2, i)
708 :     | _ => nonconst(e1, e2)
709 : monnier 409 in app emit instrs
710 :     end
711 :    
712 :     (* Round r towards zero.
713 :     * I generate the following sequence of code, which should get
714 :     * mapped into conditional moves.
715 :     *
716 :     * d <- r + i;
717 :     * d <- if (r > 0) then r else d
718 :     *)
719 : george 545 (*
720 : monnier 409 and roundToZero{ty,r,i,d} =
721 :     (doStmt(T.MV(ty,d,T.ADD(ty,T.REG(ty,r),T.LI i)));
722 :     doStmt(T.MV(ty,d,T.COND(ty,T.CMP(ty,T.GE,T.REG(ty,r),T.LI 0),
723 :     T.REG(ty,r),T.REG(ty,d))))
724 :     )
725 : george 545 *)
726 : monnier 409
727 :     (*
728 :     * Generic division.
729 :     * We first try to use the division by constant heuristic
730 :     *)
731 :     and divide(ty,pseudo,genDiv,e1,e2,rd,an) =
732 :     let fun nonconst(e1,e2) =
733 :     pseudo({ra=expr e1,rb=opn e2,rc=rd},reduceOpn)
734 :    
735 :     fun const(e,i) =
736 :     let val r = expr e
737 : george 545 in genDiv{mode=T.TO_ZERO,stm=doStmt}
738 : george 761 {r=r,i=toInt i,d=rd}
739 : monnier 409 handle _ => nonconst(T.REG(ty,r),T.LI i)
740 :     end
741 :     val instrs =
742 :     case e2 of
743 :     T.LI i => const(e1,i)
744 :     | _ => nonconst(e1,e2)
745 :     in app emit instrs
746 :     end
747 :    
748 :    
749 :     (*
750 :     and multTrap(MULV,ADD,ADDV,e1,e2,rd,an) = (* signed multiply and trap *)
751 :     let val ADD = fn {ra,rb,rc} => I.OPERATE{oper=ADD,ra=ra,rb=rb,rc=rc}
752 :     val ADDV = fn {ra,rb,rc} => I.OPERATEV{oper=ADDV,ra=ra,rb=rb,rc=rc}
753 :     val MULV = fn {ra,rb,rc} => I.OPERATEV{oper=MULV,ra=ra,rb=rb,rc=rc}
754 :     in multiply(MULV,ADD,ADDV,e1,e2,rd,an);
755 :     emit(I.TRAPB)
756 :     end
757 :    
758 :     and mulu(MUL,ADD,e1,e2,rd,an) = (* unsigned multiply *)
759 :     let val ADD = fn {ra,rb,rc} => I.OPERATE{oper=ADD,ra=ra,rb=rb,rc=rc}
760 :     val MUL = fn {ra,rb,rc} => I.OPERATE{oper=MUL,ra=ra,rb=rb,rc=rc}
761 :     in multiply(MUL,ADD,ADD,e1,e2,rd,an)
762 :     end
763 :    
764 :     (* Multiplication *)
765 :     and multiply(MULV, ADD, ADDV, e1, e2, rd, an) =
766 :     let val reg = expr e1
767 :     val opn = opn e2
768 :     fun emitMulvImmed (reg, 0, rd) =
769 :     emit(I.LDA{r=rd, b=zeroR, d=I.IMMop 0})
770 :     | emitMulvImmed (reg, 1, rd) =
771 :     emit(ADD{ra=reg, rb=zeroOpn, rc=rd})
772 :     | emitMulvImmed (reg, multiplier, rd) =
773 :     let fun log2 0w1 = 0 | log2 n = 1 + (log2 (Word.>> (n, 0w1)))
774 :     fun exp2 n = Word.<<(0w1, n)
775 :     fun bitIsSet (x,n) = Word.andb(x,exp2 n) <> 0w0
776 :     fun loop (~1) = ()
777 :     | loop n =
778 :     (if bitIsSet(itow multiplier, itow n) then
779 :     emit(ADDV{ra=reg,rb=I.REGop rd,rc=rd})
780 :     else ();
781 :     if n>0 then
782 :     emit(ADDV{ra=rd,rb=I.REGop rd,rc=rd})
783 :     else ();
784 :     loop (n-1))
785 :     in emit(ADDV{ra=reg, rb=I.REGop reg, rc=rd});
786 :     loop ((log2 (itow multiplier)) - 1)
787 :     end
788 :     in case opn of
789 :     (I.IMMop multiplier) => emitMulvImmed (reg, multiplier, rd)
790 :     | _ => mark(MULV{ra=reg, rb=opn, rc=rd},an)
791 :     (*esac*)
792 :     end
793 :     *)
794 :    
795 :     (* generate pseudo instruction *)
796 :     and pseudo(instr,e1,e2,rc) =
797 :     app emit (instr({ra=expr e1,rb=opn e2,rc=rc}, reduceOpn))
798 :    
799 :     (* generate a load *)
800 :     and load(ldOp,ea,d,mem,an) =
801 :     let val (base,disp) = addr ea
802 :     in mark(I.LOAD{ldOp=ldOp,r=d,b=base,d=disp,mem=mem},an) end
803 :    
804 :     (* generate a load with zero extension *)
805 :     and loadZext(ea,rd,mem,EXT,an) =
806 :     let val (b, d) = addr ea
807 :     val t1 = newReg()
808 :     val _ = mark(I.LOAD{ldOp=I.LDQ_U, r=t1, b=b, d=d, mem=mem},an);
809 :     val t2 = lda(b,d)
810 :     in emit(I.OPERATE{oper=EXT, ra=t1, rb=I.REGop t2, rc=rd}) end
811 :    
812 :     (* generate a load with sign extension *)
813 :     and loadSext(ea,rd,mem,off,EXT,shift,an) =
814 :     let val (b, d) = addr ea
815 :     val (b',d') = offset(b,d,off)
816 :     val t1 = newReg()
817 :     val t2 = newReg()
818 :     val t3 = newReg()
819 :     in mark(I.LOAD{ldOp=I.LDQ_U, r=t1, b=b, d=d, mem=mem},an);
820 :     emit(I.LDA{r=t2, b=b', d=d'});
821 :     emit(I.OPERATE{oper=EXT, ra=t1, rb=I.REGop t2, rc=t3});
822 :     emit(I.OPERATE{oper=I.SRA, ra=t3, rb=I.IMMop shift, rc=rd})
823 :     end
824 :    
825 :     (* generate a load byte with zero extension (page 4-48) *)
826 : leunga 583 and load8(ea,rd,mem,an) =
827 :     if !byteWordLoadStores then load(I.LDBU,ea,rd,mem,an)
828 :     else loadZext(ea,rd,mem,I.EXTBL,an)
829 : monnier 409
830 :     (* generate a load byte with sign extension (page 4-48) *)
831 : leunga 583 and load8s(ea,rd,mem,an) =
832 : leunga 585 if !byteWordLoadStores then load(I.LDB,ea,rd,mem,an)
833 : leunga 583 else loadSext(ea,rd,mem,1,I.EXTQH,56,an)
834 : monnier 409
835 :     (* generate a load 16 bit *)
836 : leunga 583 and load16(ea,rd,mem,an) =
837 :     if !byteWordLoadStores then load(I.LDWU,ea,rd,mem,an)
838 :     else loadZext(ea,rd,mem,I.EXTWL,an)
839 : monnier 409
840 :     (* generate a load 16 bit with sign extension *)
841 : leunga 583 and load16s(ea,rd,mem,an) =
842 : leunga 585 if !byteWordLoadStores then load(I.LDW,ea,rd,mem,an)
843 : leunga 583 else loadSext(ea,rd,mem,2,I.EXTQH,48,an)
844 : monnier 409
845 :     (* generate a load 32 bit with sign extension *)
846 :     and load32s(ea,rd,mem,an) = load(I.LDL,ea,rd,mem,an)
847 :    
848 :     (* generate a floating point load *)
849 :     and fload(ldOp,ea,d,mem,an) =
850 :     let val (base,disp) = addr ea
851 :     in mark(I.FLOAD{ldOp=ldOp,r=d,b=base,d=disp,mem=mem},an) end
852 :    
853 :     (* generate a store *)
854 :     and store(stOp,ea,data,mem,an) =
855 :     let val (base,disp) = addr ea
856 :     in mark(I.STORE{stOp=stOp,r=expr data,b=base,d=disp,mem=mem},an) end
857 :    
858 :     (* generate an store8 or store16 *)
859 :     and storeUnaligned(ea,data,mem,INS,MSK,an) =
860 :     let val (base,disp) = addr ea
861 :     val data = expr data
862 :     val t1 = newReg()
863 :     val t3 = newReg()
864 :     val t4 = newReg()
865 :     val t5 = newReg()
866 :     val _ = emit(I.LOAD{ldOp=I.LDQ_U, r=t1, b=base, d=disp, mem=mem})
867 :     val t2 = lda(base,disp)
868 :     in emit(I.OPERATE{oper=INS, ra=data, rb=I.REGop(t2), rc=t3});
869 :     emit(I.OPERATE{oper=MSK, ra=t1, rb=I.REGop(t2), rc=t4});
870 :     emit(I.OPERATE{oper=I.BIS, ra=t4, rb=I.REGop(t3), rc=t5});
871 :     mark(I.STORE{stOp=I.STQ_U, r=t5, b=base, d=disp, mem=mem},an)
872 :     end
873 :    
874 :     (* generate a store byte *)
875 :     and store8(ea,data,mem,an) =
876 : leunga 585 if !byteWordLoadStores then store(I.STB, ea, data, mem, an)
877 :     else storeUnaligned(ea,data,mem,I.INSBL,I.MSKBL,an)
878 : monnier 409
879 :     (* generate a store16 *)
880 :     and store16(ea,data,mem,an) =
881 : leunga 585 if !byteWordLoadStores then store(I.STW, ea, data, mem, an)
882 :     else storeUnaligned(ea,data,mem,I.INSWL,I.MSKWL,an)
883 : monnier 409
884 : monnier 429 (* generate conversion from floating point to integer *)
885 :     and cvtf2i(pseudo,rounding,e,rd,an) =
886 :     app emit (pseudo{mode=rounding, fs=fexpr e, rd=rd})
887 :    
888 : monnier 409 (* generate an expression and return the register that holds the result *)
889 : george 761 and expr(e) = let
890 :     fun comp() = let
891 :     val r = newReg()
892 :     in doExpr(e, r, []); r
893 :     end
894 :     in
895 :     case e
896 :     of T.REG(_, r) => r
897 :     | T.LI z => if T.I.isZero(z) then zeroR else comp()
898 : leunga 624 (* On the alpha: all 32 bit values are already sign extended.
899 :     * So no sign extension is necessary
900 :     *)
901 : george 761 | T.SX(64, 32, e) => expr e
902 :     | T.ZX(64, 32, e) => expr e
903 :     | _ => comp()
904 :     end
905 : leunga 624
906 : monnier 409 (* generate an expression that targets register d *)
907 : monnier 429 and doExpr(exp,d,an) =
908 :     case exp of
909 : monnier 409 T.REG(_,r) => move(r,d,an)
910 :     | T.LI n => loadImmed(n,zeroR,d,an)
911 : leunga 775 | T.LABEL l => loadLabexp(exp,d,an)
912 :     | T.CONST c => loadLabexp(exp,d,an)
913 :     | T.LABEXP le => loadLabexp(le,d,an)
914 : monnier 409
915 :     (* special optimizations for additions and subtraction
916 :     * Question: using LDA for all widths is not really correct
917 :     * since the result may not fit into the sign extension scheme.
918 :     *)
919 : leunga 775 | T.ADD(64,e,T.LABEXP le) => mark(I.LDA{r=d,b=expr e,d=I.LABop le},an)
920 :     | T.ADD(64,T.LABEXP le,e) => mark(I.LDA{r=d,b=expr e,d=I.LABop le},an)
921 :     | T.ADD(64,e,x as (T.CONST _ | T.LABEL _)) =>
922 :     mark(I.LDA{r=d,b=expr e,d=I.LABop x},an)
923 :     | T.ADD(64,x as (T.CONST _ | T.LABEL _),e) =>
924 :     mark(I.LDA{r=d,b=expr e,d=I.LABop x},an)
925 : monnier 429 | T.ADD(64,e,T.LI i) => loadImmed(i, expr e, d, an)
926 :     | T.ADD(64,T.LI i,e) => loadImmed(i, expr e, d, an)
927 : george 761 | T.SUB(sz, a, b as T.LI z) =>
928 :     if T.I.isZero(z) then
929 :     doExpr(a,d,an)
930 :     else (case sz
931 :     of 32 => minus(32,I.SUBL,I.S4SUBL,I.S8SUBL,a,b,d,an)
932 :     | 64 => minus(64,I.SUBQ,I.S4SUBQ,I.S8SUBQ,a,b,d,an)
933 :     | _ => doExpr(Gen.compileRexp exp,d,an)
934 :     (*esac*))
935 : monnier 409
936 :     (* 32-bit support *)
937 :     | T.ADD(32,a,b) => plus(32,I.ADDL,I.S4ADDL,I.S8ADDL,a,b,d,an)
938 :     | T.SUB(32,a,b) => minus(32,I.SUBL,I.S4SUBL,I.S8SUBL,a,b,d,an)
939 :     | T.ADDT(32,a,b) => commArithTrap(I.ADDLV,a,b,d,an)
940 :     | T.SUBT(32,a,b) => arithTrap(I.SUBLV,a,b,d,an)
941 : monnier 429 | T.MULT(32,a,b) =>
942 : monnier 409 multiply(32,
943 :     fn{ra,rb,rc} => I.OPERATEV{oper=I.MULLV,ra=ra,rb=rb,rc=rc},
944 :     Mult32.multiply,a,b,d,trapb,an)
945 : monnier 429 | T.MULU(32,a,b) =>
946 : monnier 409 multiply(32,
947 :     fn{ra,rb,rc} => I.OPERATE{oper=I.MULL,ra=ra,rb=rb,rc=rc},
948 :     Mulu32.multiply,a,b,d,[],an)
949 : monnier 429 | T.MULS(32,a,b) =>
950 :     multiply(32,
951 :     fn{ra,rb,rc} => I.OPERATE{oper=I.MULL,ra=ra,rb=rb,rc=rc},
952 :     Muls32.multiply,a,b,d,[],an)
953 :     | T.DIVT(32,a,b) => divide(32,P.divlv,Mult32.divide,a,b,d,an)
954 :     | T.DIVU(32,a,b) => divide(32,P.divlu,Mulu32.divide,a,b,d,an)
955 :     | T.DIVS(32,a,b) => divide(32,P.divl,Muls32.divide,a,b,d,an)
956 :     | T.REMT(32,a,b) => pseudo(P.remlv,a,b,d)
957 :     | T.REMU(32,a,b) => pseudo(P.remlu,a,b,d)
958 :     | T.REMS(32,a,b) => pseudo(P.reml,a,b,d)
959 :    
960 : monnier 409 | T.SLL(32,a,b) => sll32(a,b,d,an)
961 : leunga 796 | T.SRA(32,a,b) => sra(a,b,d,an)
962 : monnier 409 | T.SRL(32,a,b) => srl32(a,b,d,an)
963 :    
964 :     (* 64 bit support *)
965 :     | T.ADD(64,a,b) => plus(64,I.ADDQ,I.S4ADDQ,I.S8ADDQ,a,b,d,an)
966 :     | T.SUB(64,a,b) => minus(64,I.SUBQ,I.S4SUBQ,I.S8SUBQ,a,b,d,an)
967 :     | T.ADDT(64,a,b) => commArithTrap(I.ADDQV,a,b,d,an)
968 :     | T.SUBT(64,a,b) => arithTrap(I.SUBQV,a,b,d,an)
969 : monnier 429 | T.MULT(64,a,b) =>
970 : monnier 409 multiply(64,
971 :     fn{ra,rb,rc} => I.OPERATEV{oper=I.MULQV,ra=ra,rb=rb,rc=rc},
972 :     Mult64.multiply,a,b,d,trapb,an)
973 : monnier 429 | T.MULU(64,a,b) =>
974 : monnier 409 multiply(64,
975 :     fn{ra,rb,rc} => I.OPERATE{oper=I.MULQ,ra=ra,rb=rb,rc=rc},
976 :     Mulu64.multiply,a,b,d,[],an)
977 : monnier 429 | T.MULS(64,a,b) =>
978 :     multiply(64,
979 :     fn{ra,rb,rc} => I.OPERATE{oper=I.MULQ,ra=ra,rb=rb,rc=rc},
980 :     Muls64.multiply,a,b,d,[],an)
981 :     | T.DIVT(64,a,b) => divide(64,P.divqv,Mult64.divide,a,b,d,an)
982 :     | T.DIVU(64,a,b) => divide(64,P.divqu,Mulu64.divide,a,b,d,an)
983 :     | T.DIVS(64,a,b) => divide(64,P.divq,Muls64.divide,a,b,d,an)
984 :     | T.REMT(64,a,b) => pseudo(P.remqv,a,b,d)
985 :     | T.REMU(64,a,b) => pseudo(P.remqu,a,b,d)
986 :     | T.REMS(64,a,b) => pseudo(P.remq,a,b,d)
987 :    
988 : monnier 409 | T.SLL(64,a,b) => sll64(a,b,d,an)
989 : leunga 796 | T.SRA(64,a,b) => sra(a,b,d,an)
990 : monnier 409 | T.SRL(64,a,b) => srl64(a,b,d,an)
991 :    
992 :     (* special bit operations with complement *)
993 :     | T.ANDB(_,a,T.NOTB(_,b)) => arith(I.BIC,a,b,d,an)
994 :     | T.ORB(_,a,T.NOTB(_,b)) => arith(I.ORNOT,a,b,d,an)
995 :     | T.XORB(_,a,T.NOTB(_,b)) => commArith(I.EQV,a,b,d,an)
996 :     | T.ANDB(_,T.NOTB(_,a),b) => arith(I.BIC,b,a,d,an)
997 :     | T.ORB(_,T.NOTB(_,a),b) => arith(I.ORNOT,b,a,d,an)
998 :     | T.XORB(_,T.NOTB(_,a),b) => commArith(I.EQV,b,a,d,an)
999 :     | T.NOTB(_,T.XORB(_,a,b)) => commArith(I.EQV,b,a,d,an)
1000 :    
1001 :     (* bit operations *)
1002 :     | T.ANDB(ty,a,b) => andb(ty,a,b,d,an)
1003 :     | T.XORB(_,a,b) => commArith(I.XOR,a,b,d,an)
1004 :     | T.ORB(_,a,b) => commArith(I.BIS,a,b,d,an)
1005 :     | T.NOTB(_,e) => arith(I.ORNOT,zeroT,e,d,an)
1006 :    
1007 :     (* loads *)
1008 : leunga 744 | T.SX(_,_,T.LOAD(8,ea,mem)) => load8s(ea,d,mem,an)
1009 :     | T.SX(_,_,T.LOAD(16,ea,mem))=> load16s(ea,d,mem,an)
1010 :     | T.SX(_,_,T.LOAD(32,ea,mem))=> load32s(ea,d,mem,an)
1011 :     | T.ZX((8|16|32|64),_,T.LOAD(8,ea,mem)) => load8(ea,d,mem,an)
1012 :     | T.ZX((16|32|64),_,T.LOAD(16,ea,mem))=> load16(ea,d,mem,an)
1013 :     | T.ZX(64,_,T.LOAD(64,ea,mem)) => load(I.LDQ,ea,d,mem,an)
1014 : monnier 409 | T.LOAD(8,ea,mem) => load8(ea,d,mem,an)
1015 :     | T.LOAD(16,ea,mem) => load16(ea,d,mem,an)
1016 : monnier 429 | T.LOAD(32,ea,mem) => load32s(ea,d,mem,an)
1017 : monnier 409 | T.LOAD(64,ea,mem) => load(I.LDQ,ea,d,mem,an)
1018 :    
1019 : monnier 429 (* floating -> int conversion *)
1020 : monnier 475 | T.CVTF2I(ty,rounding,fty,e) =>
1021 :     (case (fty,ty) of
1022 : monnier 429 (32,32) => cvtf2i(P.cvtsl,rounding,e,d,an)
1023 :     | (32,64) => cvtf2i(P.cvtsq,rounding,e,d,an)
1024 :     | (64,32) => cvtf2i(P.cvttl,rounding,e,d,an)
1025 :     | (64,64) => cvtf2i(P.cvttq,rounding,e,d,an)
1026 : george 545 | _ => doExpr(Gen.compileRexp exp,d,an) (* other cases *)
1027 : monnier 429 )
1028 :    
1029 : monnier 409 (* conversion to boolean *)
1030 : george 761 | T.COND(_, T.CMP(ty,cond,e1,e2), x, y) =>
1031 :     (case (x, y)
1032 :     of (T.LI n, T.LI m) =>
1033 :     if EQ(n, int_1) andalso EQ(m, int_0) then
1034 :     compare(ty,cond,e1,e2,d,an)
1035 :     else if EQ(n, int_0) andalso EQ(m, int_1) then
1036 :     compare(ty,T.Basis.negateCond cond,e1,e2,d,an)
1037 :     else
1038 :     cmove(ty,cond,e1,e2,x,y,d,an)
1039 :     | _ => cmove(ty,cond,e1,e2,x,y,d,an)
1040 :     (*esac*))
1041 : monnier 409
1042 : george 545 | T.LET(s,e) => (doStmt s; doExpr(e, d, an))
1043 :     | T.MARK(e,A.MARKREG f) => (f d; doExpr(e,d,an))
1044 :     | T.MARK(e,a) => doExpr(e,d,a::an)
1045 : monnier 475 (* On the alpha: all 32 bit values are already sign extended.
1046 :     * So no sign extension is necessary
1047 :     *)
1048 : leunga 744 | T.SX(64, 32, e) => doExpr(e, d, an)
1049 :     | T.ZX(64, 32, e) => doExpr(e, d, an)
1050 : george 545
1051 :     | T.PRED(e, c) => doExpr(e, d, A.CTRLUSE c::an)
1052 : george 555 | T.REXT e => ExtensionComp.compileRext (reducer()) {e=e, an=an, rd=d}
1053 : monnier 429
1054 :     (* Defaults *)
1055 : george 545 | e => doExpr(Gen.compileRexp e,d,an)
1056 : monnier 409
1057 :     (* Hmmm... this is the funky thing described in the comments
1058 :     * in at the top of the file. This should be made parametrizable
1059 :     * for other backends.
1060 :     *)
1061 : george 545 and farith(opcode,opcodeSMLNJ,a,b,d,an) =
1062 : monnier 409 let val fa = fexpr a
1063 :     val fb = fexpr b
1064 : george 545 in if SMLNJfloatingPoint then
1065 :     (emit(I.DEFFREG d);
1066 :     mark(I.FOPERATEV{oper=opcodeSMLNJ,fa=fa,fb=fb,fc=d},an);
1067 :     emit(I.TRAPB)
1068 :     )
1069 :     else mark(I.FOPERATE{oper=opcode,fa=fa,fb=fb,fc=d},an)
1070 : monnier 409 end
1071 :    
1072 : george 545 and farith'(opcode,a,b,d,an) =
1073 :     mark(I.FOPERATE{oper=opcode,fa=fexpr a,fb=fexpr b,fc=d},an)
1074 :    
1075 : monnier 429 and funary(opcode,e,d,an) = mark(I.FUNARY{oper=opcode,fb=fexpr e,fc=d},an)
1076 :    
1077 :    
1078 : monnier 409 (* generate an floating point expression
1079 :     * return the register that holds the result
1080 :     *)
1081 :     and fexpr(T.FREG(_,r)) = r
1082 :     | fexpr e = let val d = newFreg() in doFexpr(e,d,[]); d end
1083 :    
1084 :     (* generate an external floating point operation *)
1085 : monnier 429 and fcvti2f(pseudo,e,fd,an) =
1086 : monnier 409 let val opnd = opn e
1087 : monnier 429 in app emit (pseudo({opnd=opnd, fd=fd}, reduceOpn))
1088 : monnier 409 end
1089 :    
1090 :     (* generate a floating point store *)
1091 :     and fstore(stOp,ea,data,mem,an) =
1092 :     let val (base,disp) = addr ea
1093 :     in mark(I.FSTORE{stOp=stOp,r=fexpr data,b=base,d=disp,mem=mem},an)
1094 :     end
1095 :    
1096 :     (* generate a floating point expression that targets register d *)
1097 :     and doFexpr(e,d,an) =
1098 :     case e of
1099 :     T.FREG(_,f) => fmove(f,d,an)
1100 :    
1101 :     (* single precision support *)
1102 : george 545 | T.FADD(32,a,b) => farith(I.ADDS,ADDSX,a,b,d,an)
1103 :     | T.FSUB(32,a,b) => farith(I.SUBS,SUBSX,a,b,d,an)
1104 :     | T.FMUL(32,a,b) => farith(I.MULS,MULSX,a,b,d,an)
1105 :     | T.FDIV(32,a,b) => farith(I.DIVS,DIVSX,a,b,d,an)
1106 : monnier 409
1107 :     (* double precision support *)
1108 : george 545 | T.FADD(64,a,b) => farith(I.ADDT,ADDTX,a,b,d,an)
1109 :     | T.FSUB(64,a,b) => farith(I.SUBT,SUBTX,a,b,d,an)
1110 :     | T.FMUL(64,a,b) => farith(I.MULT,MULTX,a,b,d,an)
1111 :     | T.FDIV(64,a,b) => farith(I.DIVT,DIVTX,a,b,d,an)
1112 : monnier 409
1113 : george 545 (* copy sign (correct?) XXX *)
1114 :     | T.FCOPYSIGN(_,T.FNEG(_,a),b) => farith'(I.CPYSN,a,b,d,an)
1115 :     | T.FCOPYSIGN(_,a,T.FNEG(_,b)) => farith'(I.CPYSN,a,b,d,an)
1116 :     | T.FNEG(_,T.FCOPYSIGN(_,a,b)) => farith'(I.CPYSN,a,b,d,an)
1117 :     | T.FCOPYSIGN(_,a,b) => farith'(I.CPYS,a,b,d,an)
1118 : monnier 429
1119 : monnier 409 (* generic *)
1120 :     | T.FABS(_,a) =>
1121 :     mark(I.FOPERATE{oper=I.CPYS,fa=zeroFR,fb=fexpr a,fc=d},an)
1122 :     | T.FNEG(_,a) =>
1123 :     let val fs = fexpr a
1124 :     in mark(I.FOPERATE{oper=I.CPYSN,fa=fs,fb=fs,fc=d},an) end
1125 :     | T.FSQRT(_,a) => error "fsqrt"
1126 :    
1127 :     (* loads *)
1128 :     | T.FLOAD(32,ea,mem) => fload(I.LDS,ea,d,mem,an)
1129 :     | T.FLOAD(64,ea,mem) => fload(I.LDT,ea,d,mem,an)
1130 : monnier 429
1131 :     (* floating/floating conversion
1132 :     * Note: it is not necessary to convert single precision
1133 :     * to double on the alpha.
1134 :     *)
1135 : george 545 | T.CVTF2F(fty,fty',e) => (* ignore rounding mode for now *)
1136 : monnier 475 (case (fty,fty') of
1137 : monnier 429 (64,64) => doFexpr(e,d,an)
1138 :     | (64,32) => doFexpr(e,d,an)
1139 :     | (32,32) => doFexpr(e,d,an)
1140 :     | (32,64) => funary(I.CVTTS,e,d,an) (* use normal rounding *)
1141 :     | _ => error "CVTF2F"
1142 :     )
1143 : monnier 409
1144 : monnier 429 (* integer -> floating point conversion *)
1145 : george 545 | T.CVTI2F(fty,ty,e) =>
1146 : monnier 429 let val pseudo =
1147 : monnier 475 case (ty,fty) of
1148 : monnier 429 (ty,32) => if ty <= 32 then P.cvtls else P.cvtqs
1149 :     | (ty,64) => if ty <= 32 then P.cvtlt else P.cvtqt
1150 :     | _ => error "CVTI2F"
1151 :     in fcvti2f(pseudo,e,d,an) end
1152 :    
1153 : george 545 | T.FMARK(e,A.MARKREG f) => (f d; doFexpr(e,d,an))
1154 :     | T.FMARK(e,a) => doFexpr(e,d,a::an)
1155 :     | T.FPRED(e,c) => doFexpr(e, d, A.CTRLUSE c::an)
1156 : george 555 | T.FEXT e => ExtensionComp.compileFext (reducer()) {e=e, fd=d, an=an}
1157 : monnier 409 | _ => error "doFexpr"
1158 :    
1159 :     (* check whether an expression is andb(e,1) *)
1160 : george 761 and isAndb1(e as T.ANDB(_, e1, e2)) = let
1161 :     fun isOne(n, ei) =
1162 :     if EQ(n, int_1) then (true, ei) else (false, e)
1163 :     in
1164 :     case(e1, e2)
1165 :     of (T.LI n, _) => isOne(n, e2)
1166 :     | (_, T.LI n) => isOne(n, e1)
1167 :     | _ => (false, e)
1168 :     end
1169 :     | isAndb1 e = (false, e)
1170 : monnier 409
1171 : george 761 and zeroOrOne(T.LI n) =
1172 :     if T.I.isZero n then ZERO
1173 :     else if EQ(n, int_1) then ONE
1174 :     else OTHER
1175 :     | zeroOrOne _ = OTHER
1176 : monnier 409
1177 :     (* compile a branch *)
1178 : george 545 and branch(e,lab,an) =
1179 : monnier 409 case e of
1180 :     T.CMP(ty,cc,e1 as T.LI _,e2) =>
1181 : george 545 branchBS(ty,T.Basis.swapCond cc,e2,e1,lab,an)
1182 : monnier 409 | T.CMP(ty,cc,e1,e2) => branchBS(ty,cc,e1,e2,lab,an)
1183 : george 545 (* generate an floating point branch *)
1184 :     | T.FCMP(fty,cc,e1,e2) =>
1185 :     let val f1 = fexpr e1
1186 :     val f2 = fexpr e2
1187 :     fun bcc(cmp,br) =
1188 :     let val tmpR = C.newFreg()
1189 :     in emit(I.DEFFREG(tmpR));
1190 :     emit(I.FOPERATE{oper=cmp,fa=f1,fb=f2,fc=tmpR});
1191 :     emit(I.TRAPB);
1192 :     mark(I.FBRANCH{b=br,f=tmpR,lab=lab},an)
1193 :     end
1194 :     fun fall(cmp1, br1, cmp2, br2) =
1195 :     let val tmpR1 = newFreg()
1196 :     val tmpR2 = newFreg()
1197 :     val fallLab = Label.newLabel ""
1198 :     in emit(I.DEFFREG(tmpR1));
1199 :     emit(I.FOPERATE{oper=cmp1, fa=f1, fb=f2, fc=tmpR1});
1200 :     emit(I.TRAPB);
1201 :     mark(I.FBRANCH{b=br1, f=tmpR1, lab=fallLab},an);
1202 :     emit(I.DEFFREG(tmpR2));
1203 :     emit(I.FOPERATE{oper=cmp2, fa=f1, fb=f2, fc=tmpR2});
1204 :     emit(I.TRAPB);
1205 :     mark(I.FBRANCH{b=br2, f=tmpR2, lab=lab},an);
1206 :     defineLabel fallLab
1207 :     end
1208 :     fun bcc2(cmp1, br1, cmp2, br2) =
1209 :     (bcc(cmp1, br1); bcc(cmp2, br2))
1210 :     in case cc of
1211 :     T.== => bcc(I.CMPTEQSU, I.FBNE)
1212 :     | T.?<> => bcc(I.CMPTEQSU, I.FBEQ)
1213 :     | T.? => bcc(I.CMPTUNSU, I.FBNE)
1214 :     | T.<=> => bcc(I.CMPTUNSU, I.FBEQ)
1215 :     | T.> => fall(I.CMPTLESU, I.FBNE, I.CMPTUNSU, I.FBEQ)
1216 :     | T.>= => fall(I.CMPTLTSU, I.FBNE, I.CMPTUNSU, I.FBEQ)
1217 :     | T.?> => bcc(I.CMPTLESU, I.FBEQ)
1218 :     | T.?>= => bcc(I.CMPTLTSU, I.FBEQ)
1219 :     | T.< => bcc(I.CMPTLTSU, I.FBNE)
1220 :     | T.<= => bcc(I.CMPTLESU, I.FBNE)
1221 :     | T.?< => bcc2(I.CMPTLTSU, I.FBNE, I.CMPTUNSU, I.FBNE)
1222 : leunga 744 | T.?<= => bcc2(I.CMPTLESU, I.FBNE, I.CMPTUNSU, I.FBNE)
1223 :     | T.<> => fall(I.CMPTEQSU, I.FBNE, I.CMPTUNSU, I.FBEQ)
1224 :     | T.?= => bcc2(I.CMPTEQSU, I.FBNE, I.CMPTUNSU, I.FBNE)
1225 :     | _ => error "branch"
1226 : george 545 end
1227 :     | e => mark(I.BRANCH{b=I.BNE,r=ccExpr e,lab=lab},an)
1228 : monnier 409
1229 : george 545 and br(opcode,exp,lab,an) = mark(I.BRANCH{b=opcode,r=expr exp,lab=lab},an)
1230 : monnier 409
1231 :     (* Use the branch on bit set/clear instruction when possible *)
1232 :     and branchBS(ty,cc,a,b,lab,an) =
1233 :     (case (cc,isAndb1 a,zeroOrOne b) of
1234 :     (T.EQ,(true,e),ONE) => br(I.BLBS,e,lab,an)
1235 :     | (T.EQ,(true,e),ZERO) => br(I.BLBC,e,lab,an)
1236 :     | (T.NE,(true,e),ZERO) => br(I.BLBS,e,lab,an)
1237 :     | (T.NE,(true,e),ONE) => br(I.BLBC,e,lab,an)
1238 :     | (cc,_,_) => branchIt(ty,cc,a,b,lab,an)
1239 :     )
1240 :    
1241 :     (* generate a branch instruction.
1242 :     * Check for branch on zero as a special case
1243 :     *)
1244 : george 761
1245 :     and branchIt(ty,cc,e1,e2 as T.LI z,lab,an) =
1246 :     if T.I.isZero z then branchIt0(cc,e1,lab,an)
1247 :     else branchItOther(ty,cc,e1,e2,lab,an)
1248 : monnier 409 | branchIt(ty,cc,e1,e2,lab,an) = branchItOther(ty,cc,e1,e2,lab,an)
1249 :    
1250 :     (* generate a branch instruction.
1251 :     * This function optimizes the special case of comparison with zero.
1252 :     *)
1253 :     and branchIt0(T.EQ,e,lab,an) = br(I.BEQ,e,lab,an)
1254 :     | branchIt0(T.NE,e,lab,an) = br(I.BNE,e,lab,an)
1255 :     | branchIt0(T.GT,e,lab,an) = br(I.BGT,e,lab,an)
1256 :     | branchIt0(T.GE,e,lab,an) = br(I.BGE,e,lab,an)
1257 :     | branchIt0(T.LE,e,lab,an) = br(I.BLE,e,lab,an)
1258 :     | branchIt0(T.LT,e,lab,an) = br(I.BLT,e,lab,an)
1259 :     | branchIt0(T.GTU,e,lab,an) = br(I.BNE,e,lab,an) (* always > 0! *)
1260 :     | branchIt0(T.GEU,e,lab,an) = (* always true! *) goto(lab,an)
1261 :     | branchIt0(T.LTU,e,lab,an) = (* always false! *) ()
1262 :     | branchIt0(T.LEU,e,lab,an) = br(I.BEQ,e,lab,an) (* never < 0! *)
1263 : leunga 744 | branchIt0 _ = error "brnachIt0"
1264 : monnier 409
1265 :     (* Generate the operands for unsigned comparisons
1266 :     * Mask out high order bits whenever necessary.
1267 :     *)
1268 :     and unsignedCmpOpnds(ty,e1,e2) =
1269 :     let fun zapHi(r,mask) =
1270 :     let val d = newReg()
1271 :     in emit(I.OPERATE{oper=I.ZAP, ra=r, rb=I.IMMop mask,rc=d});
1272 :     I.REGop d
1273 :     end
1274 :    
1275 :     fun zap(opn as I.REGop r) =
1276 :     (case ty of
1277 :     8 => zapHi(r,0xfd)
1278 :     | 16 => zapHi(r,0xfc)
1279 :     | 32 => zapHi(r,0xf0)
1280 :     | 64 => opn
1281 :     | _ => error "unsignedCmpOpnds"
1282 :     )
1283 :     | zap opn = opn
1284 :     val opn1 = opn e1
1285 :     val opn2 = opn e2
1286 :     in (zap opn1,zap opn2) end
1287 :    
1288 :     (* Generate a branch *)
1289 :     and branchItOther(ty,cond,e1,e2,lab,an) =
1290 :     let val tmpR = newReg()
1291 :     fun signedCmp(cmp,br) =
1292 :     (emit(I.OPERATE{oper=cmp, ra=expr e1, rb=opn e2, rc=tmpR});
1293 : george 545 mark(I.BRANCH{b=br, r=tmpR, lab=lab},an)
1294 : monnier 409 )
1295 :     fun unsignedCmp(ty,cmp,br) =
1296 :     let val (x,y) = unsignedCmpOpnds(ty,e1,e2)
1297 :     in emit(I.OPERATE{oper=cmp,ra=reduceOpn x,rb=y,rc=tmpR});
1298 : george 545 mark(I.BRANCH{b=br, r=tmpR, lab=lab},an)
1299 : monnier 409 end
1300 :     in case cond of
1301 :     T.LT => signedCmp(I.CMPLT,I.BNE)
1302 :     | T.LE => signedCmp(I.CMPLE,I.BNE)
1303 :     | T.GT => signedCmp(I.CMPLE,I.BEQ)
1304 :     | T.GE => signedCmp(I.CMPLT,I.BEQ)
1305 :     | T.EQ => signedCmp(I.CMPEQ,I.BNE)
1306 :     | T.NE => signedCmp(I.CMPEQ,I.BEQ)
1307 :     | T.LTU => unsignedCmp(ty,I.CMPULT,I.BNE)
1308 :     | T.LEU => unsignedCmp(ty,I.CMPULE,I.BNE)
1309 :     | T.GTU => unsignedCmp(ty,I.CMPULE,I.BEQ)
1310 :     | T.GEU => unsignedCmp(ty,I.CMPULT,I.BEQ)
1311 : leunga 744 | _ => error "branchItOther"
1312 : monnier 409 end
1313 :    
1314 :     (* This function generates a conditional move:
1315 :     * d = if cond(a,b) then x else y
1316 :     * Apparently, only signed comparisons conditional moves
1317 :     * are supported on the alpha.
1318 :     *)
1319 :     and cmove(ty,cond,a,b,x,y,d,an) =
1320 : george 545 let val tmp = newReg()
1321 :     val _ = doExpr(y,tmp,[]) (* evaluate false case *)
1322 : monnier 409
1323 :     val (cond,a,b) =
1324 :     (* move the immed operand to b *)
1325 :     case a of
1326 : leunga 775 (T.LI _ | T.CONST _ | T.LABEL _ | T.LABEXP _) =>
1327 :     (T.Basis.swapCond cond,b,a)
1328 : monnier 409 | _ => (cond,a,b)
1329 :    
1330 : george 761 fun sub(a, T.LI z) =
1331 :     if T.I.isZero z then expr a else expr(T.SUB(ty,a,b))
1332 :     | sub(a,b) = expr(T.SUB(ty,a,b))
1333 : monnier 409
1334 :     fun cmp(cond,e1,e2) =
1335 : george 545 let val flag = newReg()
1336 :     in compare(ty,cond,e1,e2,flag,[]); flag end
1337 : monnier 409
1338 :     val (oper,ra,x,y) =
1339 :     case (cond,isAndb1 a,zeroOrOne b) of
1340 :     (* low bit set/clear? *)
1341 :     (T.EQ,(true,e),ONE) => (I.CMOVLBS,expr e,x,y)
1342 :     | (T.EQ,(true,e),ZERO) => (I.CMOVLBC,expr e,x,y)
1343 :     | (T.NE,(true,e),ZERO) => (I.CMOVLBS,expr e,x,y)
1344 :     | (T.NE,(true,e),ONE) => (I.CMOVLBC,expr e,x,y)
1345 :     (* signed *)
1346 :     | (T.EQ,_,_) => (I.CMOVEQ,sub(a,b),x,y)
1347 : leunga 788 | (T.NE,_,_) => (I.CMOVNE,sub(a,b),x,y)
1348 : monnier 409 | (T.GT,_,_) => (I.CMOVGT,sub(a,b),x,y)
1349 :     | (T.GE,_,_) => (I.CMOVGE,sub(a,b),x,y)
1350 :     | (T.LT,_,_) => (I.CMOVLT,sub(a,b),x,y)
1351 :     | (T.LE,_,_) => (I.CMOVLE,sub(a,b),x,y)
1352 :    
1353 :     (* unsigned: do compare then use the condition code *)
1354 :     | (T.LTU,_,_) => (I.CMOVEQ,cmp(T.GEU,a,b),x,y)
1355 :     | (T.LEU,_,_) => (I.CMOVEQ,cmp(T.GTU,a,b),x,y)
1356 :     | (T.GTU,_,_) => (I.CMOVEQ,cmp(T.LEU,a,b),x,y)
1357 :     | (T.GEU,_,_) => (I.CMOVEQ,cmp(T.LTU,a,b),x,y)
1358 : leunga 744 | _ => error "cmove"
1359 : george 545 in mark(I.CMOVE{oper=oper,ra=ra,rb=opn x,rc=tmp},an); (* true case *)
1360 :     move(tmp, d, [])
1361 : monnier 409 end
1362 :    
1363 :    
1364 :     (* This function generates a comparion between e1 and e2 and writes
1365 :     * the result to register d.
1366 :     * It'll mask out the high order 32-bits when performing
1367 :     * unsigned 32-bit integer comparisons.
1368 :     *)
1369 :     and compare(ty,cond,e1,e2,d,an) =
1370 :     let fun signedCmp(oper,a,b,d) =
1371 :     mark(I.OPERATE{oper=oper,ra=expr a,rb=opn b,rc=d},an)
1372 :     fun unsignedCmp(ty,oper,a,b,d) =
1373 :     let val (x,y) = unsignedCmpOpnds(ty,a,b)
1374 :     in mark(I.OPERATE{oper=oper,ra=reduceOpn x,rb=y,rc=d},an)
1375 :     end
1376 :     fun eq(a,b,d) =
1377 :     (case (opn a,opn b) of
1378 :     (a,I.REGop r) =>
1379 :     mark(I.OPERATE{oper=I.CMPEQ,ra=r,rb=a,rc=d},an)
1380 :     | (a,b) =>
1381 :     mark(I.OPERATE{oper=I.CMPEQ,ra=reduceOpn a,rb=b,rc=d},an)
1382 :     )
1383 :     fun neq(a,b,d) =
1384 :     let val tmp = newReg()
1385 :     in eq(a,b,tmp);
1386 :     emit(I.OPERATE{oper=I.CMPEQ,ra=tmp,rb=zeroOpn,rc=d})
1387 :     end
1388 :     val (cond,e1,e2) =
1389 :     case e1 of
1390 : leunga 775 (T.LI _ | T.CONST _ | T.LABEL _ | T.LABEXP _) =>
1391 : george 545 (T.Basis.swapCond cond,e2,e1)
1392 : monnier 409 | _ => (cond,e1,e2)
1393 :     in case cond of
1394 :     T.EQ => eq(e1,e2,d)
1395 :     | T.NE => neq(e1,e2,d)
1396 :     | T.GT => signedCmp(I.CMPLT,e2,e1,d)
1397 :     | T.GE => signedCmp(I.CMPLE,e2,e1,d)
1398 :     | T.LT => signedCmp(I.CMPLT,e1,e2,d)
1399 :     | T.LE => signedCmp(I.CMPLE,e1,e2,d)
1400 :     | T.GTU => unsignedCmp(ty,I.CMPULT,e2,e1,d)
1401 :     | T.GEU => unsignedCmp(ty,I.CMPULE,e2,e1,d)
1402 :     | T.LTU => unsignedCmp(ty,I.CMPULT,e1,e2,d)
1403 :     | T.LEU => unsignedCmp(ty,I.CMPULE,e1,e2,d)
1404 : leunga 744 | _ => error "compare"
1405 : monnier 409 end
1406 :    
1407 :     (* generate an unconditional branch *)
1408 : george 545 and goto(lab,an) = mark(I.BRANCH{b=I.BR,r=zeroR,lab=lab},an)
1409 : monnier 409
1410 :     (* generate an call instruction *)
1411 : leunga 796 and call(ea,flow,defs,uses,mem,cutTo,an) =
1412 : leunga 624 let val defs=cellset defs
1413 :     val uses=cellset uses
1414 :     val instr =
1415 :     case (ea, flow) of
1416 : leunga 775 (T.LABEL lab, [_]) =>
1417 : leunga 796 I.BSR{lab=lab,r=C.returnAddr,defs=defs,uses=uses,
1418 :     cutsTo=cutTo,mem=mem}
1419 : leunga 624 | _ => I.JSR{r=C.returnAddr,b=expr ea,
1420 : leunga 796 d=0,defs=defs,uses=uses,cutsTo=cutTo,mem=mem}
1421 : leunga 624 in mark(instr,an)
1422 : monnier 409 end
1423 :    
1424 : george 545 and doCCexpr(T.CC(_,r),d,an) = move(r,d,an)
1425 :     | doCCexpr(T.FCC(_,r),d,an) = fmove(r,d,an)
1426 : monnier 409 | doCCexpr(T.CMP(ty,cond,e1,e2),d,an) = compare(ty,cond,e1,e2,d,an)
1427 :     | doCCexpr(T.FCMP(fty,cond,e1,e2),d,an) = error "doCCexpr"
1428 : george 545 | doCCexpr(T.CCMARK(e,A.MARKREG f),d,an) = (f d; doCCexpr(e,d,an))
1429 :     | doCCexpr(T.CCMARK(e,a),d,an) = doCCexpr(e,d,a::an)
1430 : george 555 | doCCexpr(T.CCEXT e,d,an) =
1431 :     ExtensionComp.compileCCext (reducer()) {e=e, ccd=d, an=an}
1432 : george 545 | doCCexpr _ = error "doCCexpr"
1433 : monnier 409
1434 : george 545 and ccExpr(T.CC(_,r)) = r
1435 :     | ccExpr(T.FCC(_,r)) = r
1436 : monnier 409 | ccExpr e = let val d = newReg()
1437 :     in doCCexpr(e,d,[]); d end
1438 :    
1439 :     (* compile a statement *)
1440 :     and stmt(s,an) =
1441 :     case s of
1442 :     T.MV(ty,r,e) => doExpr(e,r,an)
1443 :     | T.FMV(ty,r,e) => doFexpr(e,r,an)
1444 :     | T.CCMV(r,e) => doCCexpr(e,r,an)
1445 :     | T.COPY(ty,dst,src) => copy(dst,src,an)
1446 :     | T.FCOPY(ty,dst,src) => fcopy(dst,src,an)
1447 : leunga 775 | T.JMP(T.LABEL lab,_) => goto(lab,an)
1448 : leunga 744 | T.JMP(e,labs) => mark(I.JMPL({r=zeroR,b=expr e,d=0},labs),an)
1449 :     | T.BCC(cc,lab) => branch(cc,lab,an)
1450 :     | T.CALL{funct,targets,defs,uses,region,...} =>
1451 : leunga 796 call(funct,targets,defs,uses,region,[],an)
1452 :     | T.FLOW_TO(T.CALL{funct,targets,defs,uses,region,...},cutTo) =>
1453 :     call(funct,targets,defs,uses,region,cutTo,an)
1454 : leunga 628 | T.RET _ => mark(I.RET{r=zeroR,b=C.returnAddr,d=0},an)
1455 : monnier 409 | T.STORE(8,ea,data,mem) => store8(ea,data,mem,an)
1456 :     | T.STORE(16,ea,data,mem) => store16(ea,data,mem,an)
1457 :     | T.STORE(32,ea,data,mem) => store(I.STL,ea,data,mem,an)
1458 :     | T.STORE(64,ea,data,mem) => store(I.STQ,ea,data,mem,an)
1459 :     | T.FSTORE(32,ea,data,mem) => fstore(I.STS,ea,data,mem,an)
1460 :     | T.FSTORE(64,ea,data,mem) => fstore(I.STT,ea,data,mem,an)
1461 : george 545 | T.DEFINE l => defineLabel l
1462 : monnier 409 | T.ANNOTATION(s,a) => stmt(s,a::an)
1463 : george 555 | T.EXT s => ExtensionComp.compileSext (reducer()) {stm=s,an=an}
1464 : george 545 | s => doStmts (Gen.compileStm s)
1465 : monnier 409
1466 : george 545 and reducer() =
1467 :     T.REDUCER{reduceRexp = expr,
1468 :     reduceFexp = fexpr,
1469 :     reduceCCexp = ccExpr,
1470 :     reduceStm = stmt,
1471 :     operand = opn,
1472 :     reduceOperand = reduceOpn,
1473 :     addressOf = addr,
1474 :     emit = mark,
1475 :     instrStream = instrStream,
1476 :     mltreeStream = self()
1477 :     }
1478 :    
1479 : monnier 409 and doStmt s = stmt(s,[])
1480 : george 545 and doStmts ss = app doStmt ss
1481 : monnier 409
1482 : george 545 (* convert mlrisc to cellset:
1483 :     * condition code registers are mapped onto general registers
1484 :     *)
1485 :     and cellset mlrisc =
1486 :     let fun g([],acc) = acc
1487 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
1488 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
1489 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,C.addReg(cc,acc))
1490 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,C.addReg(cc,acc))
1491 :     | g(_::regs, acc) = g(regs, acc)
1492 :     in g(mlrisc, C.empty) end
1493 : monnier 409
1494 : george 545 and self() =
1495 :     S.STREAM
1496 : leunga 815 { beginCluster = beginCluster,
1497 :     endCluster = endCluster,
1498 :     emit = doStmt,
1499 :     pseudoOp = pseudoOp,
1500 :     defineLabel = defineLabel,
1501 :     entryLabel = entryLabel,
1502 :     comment = comment,
1503 :     annotation = annotation,
1504 :     getAnnotations = getAnnotations,
1505 :     exitBlock = fn regs => exitBlock(cellset regs)
1506 : george 545 }
1507 :     in self()
1508 : monnier 409 end
1509 :    
1510 :     end
1511 :    

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