Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Diff of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml
ViewVC logotype

Diff of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 1002, Fri Nov 30 17:11:33 2001 UTC revision 1003, Fri Dec 7 02:45:32 2001 UTC
# Line 140  Line 140 
140    "OpenVMS Alpha Software" (Part II of the Alpha Architecture    "OpenVMS Alpha Software" (Part II of the Alpha Architecture
141    Manual).  This stuff should apply to Unix (OSF1) as well as VMS.    Manual).  This stuff should apply to Unix (OSF1) as well as VMS.
142    
143    
144    
145    
146    
147    
148    
149                    -------------------o*o----------------------
150                               LIVE/KILL instructions
151                                     Nov 28, 2001
152                                      Lal George
153    
154      The mechanism described above is now obsolete. We no longer use
155      the DEFFREG instruction but the zero length LIVE instruction.
156      Therefore the code that gets generated is something like;
157    
158            f1 := f2 + f3
159            trap
160            LIVE f1, f2, f3
161    
162      The live ranges for f1, f2, and f3 are extended by the LIVE
163      instruction, and are live simultaneously and therefore cannot
164      be allocated to the same register.
165    
166      Multiple floating point instructions should be surrounded
167      by parallel copies. That is to say, if we have:
168    
169            f1 := f2 + f3
170            trapb
171            LIVE f1, f2, f3
172    
173            f4 := f1 * f2
174            trapb
175            LIVE f1, f2, f4
176    
177      Then the sequence above should be transformed to:
178    
179            [f2', f3'] := [f1, f2] ; parallel copy
180            f1' := f2' + f3'
181            f4' := f1' * f2'
182            trapb
183            LIVE f1', f2', f3', f4'
184            [f4] := [f4']  ; copy assuming f4 is the only value live.
185    
186      The parallel copies are to ensure that the primed variables will
187      not spill, and there should never be more than K reigsters in the LIVE
188      instruction (K is the number of registers on the machine).
189    ****************************************************************)    ****************************************************************)
190    
191    fun error msg = MLRiscErrorMsg.error("Alpha",msg)    fun error msg = MLRiscErrorMsg.error("Alpha",msg)
# Line 179  Line 225 
225       type arg  = {r1:CB.cell,r2:CB.cell,d:CB.cell}       type arg  = {r1:CB.cell,r2:CB.cell,d:CB.cell}
226       type argi = {r:CB.cell,i:int,d:CB.cell}       type argi = {r:CB.cell,i:int,d:CB.cell}
227    
228       fun mov{r,d}    = I.COPY{dst=[d],src=[r],tmp=NONE,impl=ref NONE}       fun mov{r,d}    = I.copy{dst=[d],src=[r],tmp=NONE,impl=ref NONE}
229       fun add{r1,r2,d} = I.OPERATE{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}       fun add{r1,r2,d} = I.operate{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}
230       (*       (*
231        * How to left shift by a constant (32bits)        * How to left shift by a constant (32bits)
232        *)        *)
233       fun slli{r,i=1,d} = [I.OPERATE{oper=I.ADDL,ra=r,rb=I.REGop r,rc=d}]       fun slli{r,i=1,d} = [I.operate{oper=I.ADDL,ra=r,rb=I.REGop r,rc=d}]
234         | slli{r,i=2,d} = [I.OPERATE{oper=I.S4ADDL,ra=r,rb=zeroOpn,rc=d}]         | slli{r,i=2,d} = [I.operate{oper=I.S4ADDL,ra=r,rb=zeroOpn,rc=d}]
235         | slli{r,i=3,d} = [I.OPERATE{oper=I.S8ADDL,ra=r,rb=zeroOpn,rc=d}]         | slli{r,i=3,d} = [I.operate{oper=I.S8ADDL,ra=r,rb=zeroOpn,rc=d}]
236         | slli{r,i,d}   =         | slli{r,i,d}   =
237            let val tmp = C.newReg()            let val tmp = C.newReg()
238            in  [I.OPERATE{oper=I.SLL,ra=r,rb=I.IMMop i,rc=tmp},            in  [I.operate{oper=I.SLL,ra=r,rb=I.IMMop i,rc=tmp},
239                 I.OPERATE{oper=I.ADDL,ra=tmp,rb=zeroOpn,rc=d}]                 I.operate{oper=I.ADDL,ra=tmp,rb=zeroOpn,rc=d}]
240            end            end
241    
242       (*       (*
# Line 198  Line 244 
244        *)        *)
245       fun srli{r,i,d} =       fun srli{r,i,d} =
246           let val tmp = C.newReg()           let val tmp = C.newReg()
247           in  [I.OPERATE{oper=I.ZAP,ra=r,rb=I.IMMop 0xf0,rc=tmp},           in  [I.operate{oper=I.ZAP,ra=r,rb=I.IMMop 0xf0,rc=tmp},
248                I.OPERATE{oper=I.SRL,ra=tmp,rb=I.IMMop i,rc=d}]                I.operate{oper=I.SRL,ra=tmp,rb=I.IMMop i,rc=d}]
249           end           end
250    
251       (*       (*
# Line 207  Line 253 
253        *)        *)
254       fun srai{r,i,d} =       fun srai{r,i,d} =
255           let val tmp = C.newReg()           let val tmp = C.newReg()
256           in  [I.OPERATE{oper=I.ADDL,ra=r,rb=zeroOpn,rc=tmp},           in  [I.operate{oper=I.ADDL,ra=r,rb=zeroOpn,rc=tmp},
257                I.OPERATE{oper=I.SRA,ra=tmp,rb=I.IMMop i,rc=d}]                I.operate{oper=I.SRA,ra=tmp,rb=I.IMMop i,rc=d}]
258           end           end
259      )      )
260    
# Line 222  Line 268 
268       type arg  = {r1:CB.cell, r2:CB.cell, d:CB.cell}       type arg  = {r1:CB.cell, r2:CB.cell, d:CB.cell}
269       type argi = {r:CB.cell, i:int, d:CB.cell}       type argi = {r:CB.cell, i:int, d:CB.cell}
270    
271       fun mov{r,d}    = I.COPY{dst=[d],src=[r],tmp=NONE,impl=ref NONE}       fun mov{r,d}    = I.copy{dst=[d],src=[r],tmp=NONE,impl=ref NONE}
272       fun add{r1,r2,d}= I.OPERATE{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}       fun add{r1,r2,d}= I.operate{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}
273       fun slli{r,i,d} = [I.OPERATE{oper=I.SLL,ra=r,rb=I.IMMop i,rc=d}]       fun slli{r,i,d} = [I.operate{oper=I.SLL,ra=r,rb=I.IMMop i,rc=d}]
274       fun srli{r,i,d} = [I.OPERATE{oper=I.SRL,ra=r,rb=I.IMMop i,rc=d}]       fun srli{r,i,d} = [I.operate{oper=I.SRL,ra=r,rb=I.IMMop i,rc=d}]
275       fun srai{r,i,d} = [I.OPERATE{oper=I.SRA,ra=r,rb=I.IMMop i,rc=d}]       fun srai{r,i,d} = [I.operate{oper=I.SRA,ra=r,rb=I.IMMop i,rc=d}]
276      )      )
277    
278    (* signed, trapping version of multiply and divide *)    (* signed, trapping version of multiply and divide *)
279    structure Mult32 = Multiply32    structure Mult32 = Multiply32
280      (val trapping = true      (val trapping = true
281       val multCost = multCost       val multCost = multCost
282       fun addv{r1,r2,d} = [I.OPERATEV{oper=I.ADDLV,ra=r1,rb=I.REGop r2,rc=d}]       fun addv{r1,r2,d} = [I.operatev{oper=I.ADDLV,ra=r1,rb=I.REGop r2,rc=d}]
283       fun subv{r1,r2,d} = [I.OPERATEV{oper=I.SUBLV,ra=r1,rb=I.REGop r2,rc=d}]       fun subv{r1,r2,d} = [I.operatev{oper=I.SUBLV,ra=r1,rb=I.REGop r2,rc=d}]
284       val sh1addv = NONE       val sh1addv = NONE
285       val sh2addv = NONE       val sh2addv = NONE
286       val sh3addv = NONE       val sh3addv = NONE
# Line 245  Line 291 
291    functor Mul32 = Multiply32    functor Mul32 = Multiply32
292      (val trapping = false      (val trapping = false
293       val multCost = multCost       val multCost = multCost
294       fun addv{r1,r2,d} = [I.OPERATE{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}]       fun addv{r1,r2,d} = [I.operate{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}]
295       fun subv{r1,r2,d} = [I.OPERATE{oper=I.SUBL,ra=r1,rb=I.REGop r2,rc=d}]       fun subv{r1,r2,d} = [I.operate{oper=I.SUBL,ra=r1,rb=I.REGop r2,rc=d}]
296       val sh1addv = NONE       val sh1addv = NONE
297       val sh2addv = SOME(fn {r1,r2,d} =>       val sh2addv = SOME(fn {r1,r2,d} =>
298                      [I.OPERATE{oper=I.S4ADDL,ra=r1,rb=I.REGop r2,rc=d}])                      [I.operate{oper=I.S4ADDL,ra=r1,rb=I.REGop r2,rc=d}])
299       val sh3addv = SOME(fn {r1,r2,d} =>       val sh3addv = SOME(fn {r1,r2,d} =>
300                      [I.OPERATE{oper=I.S8ADDL,ra=r1,rb=I.REGop r2,rc=d}])                      [I.operate{oper=I.S8ADDL,ra=r1,rb=I.REGop r2,rc=d}])
301      )      )
302    structure Mulu32 = Mul32(val signed = false)    structure Mulu32 = Mul32(val signed = false)
303    structure Muls32 = Mul32(val signed = true)    structure Muls32 = Mul32(val signed = true)
# Line 260  Line 306 
306    structure Mult64 = Multiply64    structure Mult64 = Multiply64
307      (val trapping = true      (val trapping = true
308       val multCost = multCost       val multCost = multCost
309       fun addv{r1,r2,d} = [I.OPERATEV{oper=I.ADDQV,ra=r1,rb=I.REGop r2,rc=d}]       fun addv{r1,r2,d} = [I.operatev{oper=I.ADDQV,ra=r1,rb=I.REGop r2,rc=d}]
310       fun subv{r1,r2,d} = [I.OPERATEV{oper=I.SUBQV,ra=r1,rb=I.REGop r2,rc=d}]       fun subv{r1,r2,d} = [I.operatev{oper=I.SUBQV,ra=r1,rb=I.REGop r2,rc=d}]
311       val sh1addv = NONE       val sh1addv = NONE
312       val sh2addv = NONE       val sh2addv = NONE
313       val sh3addv = NONE       val sh3addv = NONE
# Line 272  Line 318 
318    functor Mul64 = Multiply64    functor Mul64 = Multiply64
319      (val trapping = false      (val trapping = false
320       val multCost = multCost       val multCost = multCost
321       fun addv{r1,r2,d} = [I.OPERATE{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}]       fun addv{r1,r2,d} = [I.operate{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}]
322       fun subv{r1,r2,d} = [I.OPERATE{oper=I.SUBQ,ra=r1,rb=I.REGop r2,rc=d}]       fun subv{r1,r2,d} = [I.operate{oper=I.SUBQ,ra=r1,rb=I.REGop r2,rc=d}]
323       val sh1addv = NONE       val sh1addv = NONE
324       val sh2addv = SOME(fn {r1,r2,d} =>       val sh2addv = SOME(fn {r1,r2,d} =>
325                      [I.OPERATE{oper=I.S4ADDQ,ra=r1,rb=I.REGop r2,rc=d}])                      [I.operate{oper=I.S4ADDQ,ra=r1,rb=I.REGop r2,rc=d}])
326       val sh3addv = SOME(fn {r1,r2,d} =>       val sh3addv = SOME(fn {r1,r2,d} =>
327                      [I.OPERATE{oper=I.S8ADDQ,ra=r1,rb=I.REGop r2,rc=d}])                      [I.operate{oper=I.S8ADDQ,ra=r1,rb=I.REGop r2,rc=d}])
328      )      )
329    structure Mulu64 = Mul64(val signed = false)    structure Mulu64 = Mul64(val signed = false)
330    structure Muls64 = Mul64(val signed = true)    structure Muls64 = Mul64(val signed = true)
# Line 294  Line 340 
340    val zeroFR = C.f31    val zeroFR = C.f31
341    val zeroEA = I.Direct zeroR    val zeroEA = I.Direct zeroR
342    val zeroT  = T.LI int_0    val zeroT  = T.LI int_0
343    val trapb = [I.TRAPB]    val trapb = [I.trapb]
344    val zeroImm = I.IMMop 0    val zeroImm = I.IMMop 0
345    
346    fun selectInstructions    fun selectInstructions
347          (instrStream as          (instrStream as
348           TS.S.STREAM{emit,beginCluster,endCluster,getAnnotations,           TS.S.STREAM{emit=emitInstruction,beginCluster,endCluster,getAnnotations,
349                       defineLabel,entryLabel,pseudoOp,annotation,                       defineLabel,entryLabel,pseudoOp,annotation,
350                       exitBlock,comment,...}) =                       exitBlock,comment,...}) =
351    let    let
352    
353        infix || && << >> ~>>        infix || && << >> ~>>
354    
355        val op ||  = W32.orb        val op ||  = W32.orb
# Line 314  Line 361 
361        val itow = Word.fromInt        val itow = Word.fromInt
362        val wtoi = Word.toIntX        val wtoi = Word.toIntX
363    
364          val emit = emitInstruction o I.INSTR
365    
366        val newReg = C.newReg        val newReg = C.newReg
367        val newFreg = C.newFreg        val newFreg = C.newFreg
368    
# Line 334  Line 383 
383        val (ADDSX,SUBSX,MULSX,DIVSX) =        val (ADDSX,SUBSX,MULSX,DIVSX) =
384              (I.ADDSSUD,I.SUBSSUD,I.MULSSUD,I.DIVSSUD)              (I.ADDSSUD,I.SUBSSUD,I.MULSSUD,I.DIVSSUD)
385    
386        fun mark'(i,[]) = i        fun annotate(i, an) = List.foldl (fn (a, i) => I.ANNOTATION{i=i,a=a}) i an
387          | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)        fun mark'(i, an) = emitInstruction(annotate(i,an))
388        fun mark(i,an) = emit(mark'(i,an))        fun mark(i,an) = emitInstruction(annotate(I.INSTR i,an))
389    
390        (* Fit within 16 bits? *)        (* Fit within 16 bits? *)
391        fun literal16 n = ~32768 <= n andalso n < 32768        fun literal16 n = ~32768 <= n andalso n < 32768
# Line 695  Line 744 
744                    (i,I.REGop r) => gen{ra=r,rb=i,rc=rd}                    (i,I.REGop r) => gen{ra=r,rb=i,rc=rd}
745                  | (I.REGop r,i) => gen{ra=r,rb=i,rc=rd}                  | (I.REGop r,i) => gen{ra=r,rb=i,rc=rd}
746                  | (r,i)         => gen{ra=reduceOpn r,rb=i,rc=rd}                  | (r,i)         => gen{ra=reduceOpn r,rb=i,rc=rd}
747                in mark'(instr,an)::trapb end                in annotate(instr,an)::trapb end
748                fun const(e,i) =                fun const(e,i) =
749                    let val r = expr e                    let val r = expr e
750                    in  if !useMultByConst andalso                    in  if !useMultByConst andalso
751                             IntInf.>=(i, T.I.int_0) andalso                             IntInf.>=(i, T.I.int_0) andalso
752                             IntInf.<(i, T.I.int_0x100) then                             IntInf.<(i, T.I.int_0x100) then
753                           mark'(gen{ra=r,rb=I.IMMop(toInt i),rc=rd},an)::trapb                           annotate(gen{ra=r,rb=I.IMMop(toInt i),rc=rd},an)::trapb
754                        else                        else
755                           (genConst{r=r,i=toInt i,d=rd}@trapb                           (genConst{r=r,i=toInt i,d=rd}@trapb
756                            handle _ => nonconst(T.REG(ty,r),T.LI i))                            handle _ => nonconst(T.REG(ty,r),T.LI i))
# Line 711  Line 760 
760                  of (_, T.LI i) => const(e1, i)                  of (_, T.LI i) => const(e1, i)
761                   | (T.LI i, _) => const(e2, i)                   | (T.LI i, _) => const(e2, i)
762                   | _ => nonconst(e1, e2)                   | _ => nonconst(e1, e2)
763            in  app emit instrs            in  app emitInstruction instrs
764            end            end
765    
766            (* Round r towards zero.            (* Round r towards zero.
# Line 747  Line 796 
796                    case e2 of                    case e2 of
797                       T.LI i   => const(e1,i)                       T.LI i   => const(e1,i)
798                     | _        => nonconst(e1,e2)                     | _        => nonconst(e1,e2)
799            in  app emit instrs            in  app emitInstruction instrs
800            end            end
801    
802    
# Line 799  Line 848 
848    
849        (* generate pseudo instruction *)        (* generate pseudo instruction *)
850        and pseudo(instr,e1,e2,rc) =        and pseudo(instr,e1,e2,rc) =
851             app emit (instr({ra=expr e1,rb=opn e2,rc=rc}, reduceOpn))             app emitInstruction (instr({ra=expr e1,rb=opn e2,rc=rc}, reduceOpn))
852    
853        (* generate a load *)        (* generate a load *)
854        and load(ldOp,ea,d,mem,an) =        and load(ldOp,ea,d,mem,an) =
# Line 888  Line 937 
937    
938        (* generate conversion from floating point to integer *)        (* generate conversion from floating point to integer *)
939        and cvtf2i(pseudo,rounding,e,rd,an) =        and cvtf2i(pseudo,rounding,e,rd,an) =
940            app emit (pseudo{mode=rounding, fs=fexpr e, rd=rd})            app emitInstruction (pseudo{mode=rounding, fs=fexpr e, rd=rd})
941    
942        (* generate an expression and return the register that holds the result *)        (* generate an expression and return the register that holds the result *)
943        and expr(e) = let        and expr(e) = let
# Line 945  Line 994 
994            | T.SUBT(32,a,b) => arithTrap(I.SUBLV,a,b,d,an)            | T.SUBT(32,a,b) => arithTrap(I.SUBLV,a,b,d,an)
995            | T.MULT(32,a,b) =>            | T.MULT(32,a,b) =>
996                 multiply(32,                 multiply(32,
997                   fn{ra,rb,rc} => I.OPERATEV{oper=I.MULLV,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operatev{oper=I.MULLV,ra=ra,rb=rb,rc=rc},
998                   Mult32.multiply,a,b,d,trapb,an)                   Mult32.multiply,a,b,d,trapb,an)
999            | T.MULU(32,a,b) =>            | T.MULU(32,a,b) =>
1000                 multiply(32,                 multiply(32,
1001                   fn{ra,rb,rc} => I.OPERATE{oper=I.MULL,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operate{oper=I.MULL,ra=ra,rb=rb,rc=rc},
1002                   Mulu32.multiply,a,b,d,[],an)                   Mulu32.multiply,a,b,d,[],an)
1003            | T.MULS(32,a,b) =>            | T.MULS(32,a,b) =>
1004                 multiply(32,                 multiply(32,
1005                   fn{ra,rb,rc} => I.OPERATE{oper=I.MULL,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operate{oper=I.MULL,ra=ra,rb=rb,rc=rc},
1006                   Muls32.multiply,a,b,d,[],an)                   Muls32.multiply,a,b,d,[],an)
1007            | T.DIVT(32,a,b) => divide(32,P.divlv,Mult32.divide,a,b,d,an)            | T.DIVT(32,a,b) => divide(32,P.divlv,Mult32.divide,a,b,d,an)
1008            | T.DIVU(32,a,b) => divide(32,P.divlu,Mulu32.divide,a,b,d,an)            | T.DIVU(32,a,b) => divide(32,P.divlu,Mulu32.divide,a,b,d,an)
# Line 973  Line 1022 
1022            | T.SUBT(64,a,b) => arithTrap(I.SUBQV,a,b,d,an)            | T.SUBT(64,a,b) => arithTrap(I.SUBQV,a,b,d,an)
1023            | T.MULT(64,a,b) =>            | T.MULT(64,a,b) =>
1024                 multiply(64,                 multiply(64,
1025                   fn{ra,rb,rc} => I.OPERATEV{oper=I.MULQV,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operatev{oper=I.MULQV,ra=ra,rb=rb,rc=rc},
1026                   Mult64.multiply,a,b,d,trapb,an)                   Mult64.multiply,a,b,d,trapb,an)
1027            | T.MULU(64,a,b) =>            | T.MULU(64,a,b) =>
1028                 multiply(64,                 multiply(64,
1029                   fn{ra,rb,rc} => I.OPERATE{oper=I.MULQ,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operate{oper=I.MULQ,ra=ra,rb=rb,rc=rc},
1030                   Mulu64.multiply,a,b,d,[],an)                   Mulu64.multiply,a,b,d,[],an)
1031            | T.MULS(64,a,b) =>            | T.MULS(64,a,b) =>
1032                 multiply(64,                 multiply(64,
1033                   fn{ra,rb,rc} => I.OPERATE{oper=I.MULQ,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operate{oper=I.MULQ,ra=ra,rb=rb,rc=rc},
1034                   Muls64.multiply,a,b,d,[],an)                   Muls64.multiply,a,b,d,[],an)
1035            | T.DIVT(64,a,b) => divide(64,P.divqv,Mult64.divide,a,b,d,an)            | T.DIVT(64,a,b) => divide(64,P.divqv,Mult64.divide,a,b,d,an)
1036            | T.DIVU(64,a,b) => divide(64,P.divqu,Mulu64.divide,a,b,d,an)            | T.DIVU(64,a,b) => divide(64,P.divqu,Mulu64.divide,a,b,d,an)
# Line 1067  Line 1116 
1116            let val fa = fexpr a            let val fa = fexpr a
1117                val fb = fexpr b                val fb = fexpr b
1118            in  if SMLNJfloatingPoint then            in  if SMLNJfloatingPoint then
1119                     (emit(I.DEFFREG d);                     ((* emit(I.DEFFREG d); *)
1120                      mark(I.FOPERATEV{oper=opcodeSMLNJ,fa=fa,fb=fb,fc=d},an);                      mark(I.FOPERATEV{oper=opcodeSMLNJ,fa=fa,fb=fb,fc=d},an);
1121                      emit(I.TRAPB)                      emit(I.TRAPB);
1122                        emitInstruction(I.LIVE{regs=List.foldl C.addFreg C.empty [fa,fb,d],
1123                                               spilled=[]})
1124    
1125                     )                     )
1126                else mark(I.FOPERATE{oper=opcode,fa=fa,fb=fb,fc=d},an)                else mark(I.FOPERATE{oper=opcode,fa=fa,fb=fb,fc=d},an)
1127            end            end
# Line 1089  Line 1141 
1141        (* generate an external floating point operation *)        (* generate an external floating point operation *)
1142        and fcvti2f(pseudo,e,fd,an) =        and fcvti2f(pseudo,e,fd,an) =
1143            let val opnd = opn e            let val opnd = opn e
1144            in  app emit (pseudo({opnd=opnd, fd=fd}, reduceOpn))            in  app emitInstruction (pseudo({opnd=opnd, fd=fd}, reduceOpn))
1145            end            end
1146    
1147        (* generate a floating point store *)        (* generate a floating point store *)
# Line 1191  Line 1243 
1243                  val f2 = fexpr e2                  val f2 = fexpr e2
1244                  fun bcc(cmp,br) =                  fun bcc(cmp,br) =
1245                  let val tmpR = C.newFreg()                  let val tmpR = C.newFreg()
1246                  in  emit(I.DEFFREG(tmpR));                  in  (*emit(I.DEFFREG(tmpR));*)
1247                      emit(I.FOPERATE{oper=cmp,fa=f1,fb=f2,fc=tmpR});                      emit(I.FOPERATE{oper=cmp,fa=f1,fb=f2,fc=tmpR});
1248                      emit(I.TRAPB);                      emit(I.TRAPB);
1249                        emitInstruction(I.LIVE{regs=List.foldl C.addFreg C.empty [f1,f2,tmpR],
1250                                    spilled=[]});
1251                      mark(I.FBRANCH{b=br,f=tmpR,lab=lab},an)                      mark(I.FBRANCH{b=br,f=tmpR,lab=lab},an)
1252                  end                  end
1253                  fun fall(cmp1, br1, cmp2, br2) =                  fun fall(cmp1, br1, cmp2, br2) =
1254                  let val tmpR1 = newFreg()                  let val tmpR1 = newFreg()
1255                      val tmpR2 = newFreg()                      val tmpR2 = newFreg()
1256                      val fallLab = Label.anon()                      val fallLab = Label.anon()
1257                  in  emit(I.DEFFREG(tmpR1));                  in  (*emit(I.DEFFREG(tmpR1));*)
1258                      emit(I.FOPERATE{oper=cmp1, fa=f1, fb=f2, fc=tmpR1});                      emit(I.FOPERATE{oper=cmp1, fa=f1, fb=f2, fc=tmpR1});
1259                      emit(I.TRAPB);                      emit(I.TRAPB);
1260                        emitInstruction(I.LIVE{regs=List.foldl C.addFreg C.empty [f1,f2,tmpR1],
1261                                    spilled=[]});
1262                      mark(I.FBRANCH{b=br1, f=tmpR1, lab=fallLab},an);                      mark(I.FBRANCH{b=br1, f=tmpR1, lab=fallLab},an);
1263                      emit(I.DEFFREG(tmpR2));                      (* emit(I.DEFFREG(tmpR2)); *)
1264                      emit(I.FOPERATE{oper=cmp2, fa=f1, fb=f2, fc=tmpR2});                      emit(I.FOPERATE{oper=cmp2, fa=f1, fb=f2, fc=tmpR2});
1265                      emit(I.TRAPB);                      emit(I.TRAPB);
1266                        emitInstruction(I.LIVE{regs=List.foldl C.addFreg C.empty [f1,f2,tmpR2],
1267                                    spilled=[]});
1268                      mark(I.FBRANCH{b=br2, f=tmpR2, lab=lab},an);                      mark(I.FBRANCH{b=br2, f=tmpR2, lab=lab},an);
1269                      defineLabel fallLab                      defineLabel fallLab
1270                  end                  end
# Line 1467  Line 1525 
1525            | T.DEFINE l => defineLabel l            | T.DEFINE l => defineLabel l
1526            | T.ANNOTATION(s,a) => stmt(s,a::an)            | T.ANNOTATION(s,a) => stmt(s,a::an)
1527            | T.EXT s => ExtensionComp.compileSext (reducer()) {stm=s,an=an}            | T.EXT s => ExtensionComp.compileSext (reducer()) {stm=s,an=an}
1528              | T.LIVE rs => mark'(I.LIVE{regs=cellset rs, spilled=[]}, an)
1529              | T.KILL rs => mark'(I.KILL{regs=cellset rs, spilled=[]}, an)
1530            | s => doStmts (Gen.compileStm s)            | s => doStmts (Gen.compileStm s)
1531    
1532        and reducer() =        and reducer() =
# Line 1477  Line 1537 
1537                       operand       = opn,                       operand       = opn,
1538                       reduceOperand = reduceOpn,                       reduceOperand = reduceOpn,
1539                       addressOf     = addr,                       addressOf     = addr,
1540                       emit          = mark,                       emit          = emitInstruction o annotate,
1541                       instrStream   = instrStream,                       instrStream   = instrStream,
1542                       mltreeStream  = self()                       mltreeStream  = self()
1543                      }                      }

Legend:
Removed from v.1002  
changed lines
  Added in v.1003

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0