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[smlnj] Diff of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml
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Diff of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml

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revision 555, Fri Mar 3 16:10:30 2000 UTC revision 583, Thu Mar 23 21:52:30 2000 UTC
# Line 29  Line 29 
29         * This should be set to false for C-like clients but true for SML/NJ.         * This should be set to false for C-like clients but true for SML/NJ.
30         *)         *)
31      val SMLNJfloatingPoint : bool      val SMLNJfloatingPoint : bool
32    
33          (* Should we use generate special byte/word load instructions
34           * like LDBU, LDWU, STB, STW.
35           *)
36        val byteWordLoadStores : bool ref
37     ) : MLTREECOMP =     ) : MLTREECOMP =
38  struct  struct
39    
# Line 284  Line 289 
289    datatype zeroOne   = ZERO | ONE | OTHER    datatype zeroOne   = ZERO | ONE | OTHER
290    datatype commutative = COMMUTE | NOCOMMUTE    datatype commutative = COMMUTE | NOCOMMUTE
291    
292      val zeroFR = C.FPReg 31
293      val zeroEA = I.Direct zeroR
294      val zeroT  = T.LI 0
295      val trapb = [I.TRAPB]
296      val zeroImm = I.IMMop 0
297    
298    fun selectInstructions    fun selectInstructions
299          (instrStream as          (instrStream as
300           S.STREAM{emit,beginCluster,endCluster,           S.STREAM{emit,beginCluster,endCluster,
# Line 301  Line 312 
312        val itow = Word.fromInt        val itow = Word.fromInt
313        val wtoi = Word.toIntX        val wtoi = Word.toIntX
314    
       val zeroFR = C.FPReg 31  
       val zeroEA = I.Direct zeroR  
       val zeroT  = T.LI 0  
   
315        val newReg = C.newReg        val newReg = C.newReg
316        val newFreg = C.newFreg        val newFreg = C.newFreg
317    
       val trapb = [I.TRAPB]  
   
318        (* Choose the appropriate rounding mode to generate.        (* Choose the appropriate rounding mode to generate.
319         * This stuff is used to support the alpha32x SML/NJ backend.         * This stuff is used to support the alpha32x SML/NJ backend.
320         *         *
# Line 480  Line 485 
485          | opn(T.CONST c) = I.LABop(LE.CONST c)          | opn(T.CONST c) = I.LABop(LE.CONST c)
486          | opn e = I.REGop(expr e)          | opn e = I.REGop(expr e)
487    
488        (* compute base+displacement from an expression *)        (* compute base+displacement from an expression
489           *)
490        and addr exp =        and addr exp =
491            case exp of            let fun toLexp(I.IMMop i) = LE.INT i
492              T.ADD(_,e,T.LI n) => makeEA(expr e,n)                  | toLexp(I.LABop le) = le
493            | T.ADD(_,T.LI n,e) => makeEA(expr e,n)                  | toLexp _ = error "addr.toLexp"
494            | T.ADD(_,e,T.CONST c) => (expr e,I.LABop(LE.CONST c))  
495            | T.ADD(_,T.CONST c,e) => (expr e,I.LABop(LE.CONST c))                fun add(n,I.IMMop m) = I.IMMop(n+m)
496            | T.SUB(_,e,T.LI n) => makeEA(expr e,~n)                  | add(n,I.LABop le) = I.LABop(LE.PLUS(LE.INT n,le))
497            | e => makeEA(expr e,0)                  | add(n,_) = error "addr.add"
498                  fun add32(n,disp) = add(W32.toIntX n,disp) (* overflow XXX *)
499                  fun addC(c,I.IMMop 0) = I.LABop(LE.CONST c)
500                    | addC(c,disp) = I.LABop(LE.PLUS(LE.CONST c,toLexp disp))
501                  fun addL(l,I.IMMop 0) = I.LABop l
502                    | addL(l,disp) = I.LABop(LE.PLUS(l,toLexp disp))
503                  fun sub(n,I.IMMop m) = I.IMMop(m-n)
504                    | sub(n,I.LABop le) = I.LABop(LE.MINUS(le,LE.INT n))
505                    | sub(n,_) = error "addr.sub"
506                  fun sub32(n,disp) = sub(W32.toIntX n,disp)
507                  fun subC(c,disp) = I.LABop(LE.MINUS(toLexp disp, LE.CONST c))
508                  fun subL(l,disp) = I.LABop(LE.MINUS(toLexp disp, l))
509    
510                  (* Should really take into account of the address width XXX *)
511                  fun fold(T.ADD(_,e,T.LI n),disp) = fold(e, add(n,disp))
512                    | fold(T.ADD(_,e,T.LI32 n),disp) = fold(e, add32(n,disp))
513                    | fold(T.ADD(_,e,T.CONST c),disp) = fold(e, addC(c,disp))
514                    | fold(T.ADD(_,e,T.LABEL l),disp) = fold(e, addL(l,disp))
515                    | fold(T.ADD(_,T.LI n,e),disp) = fold(e, add(n,disp))
516                    | fold(T.ADD(_,T.LI32 n, e),disp) = fold(e, add32(n,disp))
517                    | fold(T.ADD(_,T.CONST n, e),disp) = fold(e, addC(n,disp))
518                    | fold(T.ADD(_,T.LABEL l, e),disp) = fold(e, addL(l,disp))
519                    | fold(T.SUB(_,e,T.LI n),disp) = fold(e, sub(n,disp))
520                    | fold(T.SUB(_,e,T.LI32 n),disp) = fold(e, sub32(n,disp))
521                    | fold(T.SUB(_,e,T.CONST n),disp) = fold(e, subC(n,disp))
522                    | fold(T.SUB(_,e,T.LABEL l),disp) = fold(e, subL(l,disp))
523                    | fold(e,disp) = (expr e,disp)
524    
525              in  makeEA(fold(exp, zeroImm))
526              end
527    
528        (* compute base+displacement+small offset *)        (* compute base+displacement+small offset *)
529        and offset(base,disp as I.IMMop n,off) =        and offset(base,disp as I.IMMop n,off) =
# Line 500  Line 535 
535                     (tmp,I.IMMop off)                     (tmp,I.IMMop off)
536                 end                 end
537             end             end
538            | offset(base,disp as I.LABop le,off) =
539               (base, I.LABop(LE.PLUS(le,LE.INT off)))
540          | offset(base,disp,off) =          | offset(base,disp,off) =
541             let val tmp = newReg()             let val tmp = newReg()
542             in  emit(I.OPERATE{oper=I.ADDQ,ra=base,rb=disp,rc=tmp});             in  emit(I.OPERATE{oper=I.ADDQ,ra=base,rb=disp,rc=tmp});
543                 (tmp,I.IMMop off)                 (tmp,I.IMMop off)
544             end             end
545    
546        (* check if base offset *)        (* check if base offset fits within the field *)
547        and makeEA(base, offset) =        and makeEA(base, off as I.IMMop offset) =
548           if ~32768 <= offset andalso offset <= 32767 then (base, I.IMMop offset)           if ~32768 <= offset andalso offset <= 32767
549             then (base, off)
550           else           else
551           let val tmpR = newReg()           let val tmpR = newReg()
552                  (* unsigned low 16 bits *)                  (* unsigned low 16 bits *)
# Line 520  Line 558 
558               (emit(I.LDAH{r=tmpR, b=base, d=I.IMMop highsgn});               (emit(I.LDAH{r=tmpR, b=base, d=I.IMMop highsgn});
559               (tmpR, I.IMMop lowsgn))               (tmpR, I.IMMop lowsgn))
560           end           end
561           | makeEA(base, offset) = (base, offset)
562    
563        (* look for multiply by 4 and 8 of the given type *)        (* look for multiply by 4 and 8 of the given type *)
564        and times4or8(ty,e) =        and times4or8(ty,e) =
# Line 799  Line 838 
838            let val (base,disp) = addr ea            let val (base,disp) = addr ea
839            in  mark(I.LOAD{ldOp=ldOp,r=d,b=base,d=disp,mem=mem},an) end            in  mark(I.LOAD{ldOp=ldOp,r=d,b=base,d=disp,mem=mem},an) end
840    
841          (* generate a load and sign extension *)
842          and loadSigned(ldOp,bits,ea,rd,mem,an) =
843              let val t1 = newReg()
844                  val t2 = newReg()
845                  val shift = I.IMMop(64-bits)
846              in  load(ldOp,ea,t1,mem,an);
847                  emit(I.OPERATE{oper=I.SLL, ra=t1, rb=shift, rc=t2});
848                  emit(I.OPERATE{oper=I.SRA, ra=t2, rb=shift, rc=rd})
849              end
850    
851        (* generate a load with zero extension *)        (* generate a load with zero extension *)
852        and loadZext(ea,rd,mem,EXT,an) =        and loadZext(ea,rd,mem,EXT,an) =
853            let val (b, d) = addr ea            let val (b, d) = addr ea
# Line 821  Line 870 
870            end            end
871    
872        (* generate a load byte with zero extension (page 4-48) *)        (* generate a load byte with zero extension (page 4-48) *)
873        and load8(ea,rd,mem,an) = loadZext(ea,rd,mem,I.EXTBL,an)        and load8(ea,rd,mem,an) =
874              if !byteWordLoadStores then load(I.LDBU,ea,rd,mem,an)
875              else loadZext(ea,rd,mem,I.EXTBL,an)
876    
877        (* generate a load byte with sign extension (page 4-48) *)        (* generate a load byte with sign extension (page 4-48) *)
878        and load8s(ea,rd,mem,an) = loadSext(ea,rd,mem,1,I.EXTQH,56,an)        and load8s(ea,rd,mem,an) =
879              if !byteWordLoadStores then loadSigned(I.LDBU,8,ea,rd,mem,an)
880              else loadSext(ea,rd,mem,1,I.EXTQH,56,an)
881    
882        (* generate a load 16 bit *)        (* generate a load 16 bit *)
883        and load16(ea,rd,mem,an) = loadZext(ea,rd,mem,I.EXTWL,an)        and load16(ea,rd,mem,an) =
884              if !byteWordLoadStores then load(I.LDWU,ea,rd,mem,an)
885              else loadZext(ea,rd,mem,I.EXTWL,an)
886    
887        (* generate a load 16 bit with sign extension *)        (* generate a load 16 bit with sign extension *)
888        and load16s(ea,rd,mem,an) = loadSext(ea,rd,mem,2,I.EXTQH,48,an)        and load16s(ea,rd,mem,an) =
889              if !byteWordLoadStores then loadSigned(I.LDWU,16,ea,rd,mem,an)
890              else loadSext(ea,rd,mem,2,I.EXTQH,48,an)
891    
892        (* generate a load 32 bit with sign extension *)        (* generate a load 32 bit with sign extension *)
893        and load32s(ea,rd,mem,an) = load(I.LDL,ea,rd,mem,an)        and load32s(ea,rd,mem,an) = load(I.LDL,ea,rd,mem,an)

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