Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Diff of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml
ViewVC logotype

Diff of /sml/trunk/src/MLRISC/alpha/mltree/alpha.sml

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 788, Wed Feb 28 04:09:48 2001 UTC revision 1009, Wed Jan 9 19:44:22 2002 UTC
# Line 5  Line 5 
5   *   *
6   * -- Allen   * -- Allen
7   *   *
8   * Notes: places with optimizations are marked ***OPT***   * Notes: places with optimizations are marked ***OPT**n*
9   *)   *)
10    
11    
12  functor Alpha  functor Alpha
13     (structure AlphaInstr : ALPHAINSTR     (structure AlphaInstr : ALPHAINSTR
14      structure PseudoInstrs : ALPHA_PSEUDO_INSTR      structure PseudoInstrs : ALPHA_PSEUDO_INSTR
15                            where I = AlphaInstr
16      structure ExtensionComp : MLTREE_EXTENSION_COMP      structure ExtensionComp : MLTREE_EXTENSION_COMP
17         where I = AlphaInstr         where I = AlphaInstr
18         sharing PseudoInstrs.I = AlphaInstr                            and T = AlphaInstr.T
19    
20        (* Cost of multiplication in cycles *)        (* Cost of multiplication in cycles *)
21      val multCost : int ref      val multCost : int ref
# Line 36  Line 38 
38    structure I   = AlphaInstr    structure I   = AlphaInstr
39    structure C   = I.C    structure C   = I.C
40    structure T   = I.T    structure T   = I.T
41    structure S   = T.Stream    structure TS  = ExtensionComp.TS
42    structure R   = T.Region    structure R   = T.Region
43    structure W32 = Word32    structure W32 = Word32
44    structure P   = PseudoInstrs    structure P   = PseudoInstrs
45    structure A   = MLRiscAnnotations    structure A   = MLRiscAnnotations
46      structure CB  = CellsBasis
47      structure CFG = ExtensionComp.CFG
48    
49   (*********************************************************   (*********************************************************
50    
# Line 137  Line 141 
141    "OpenVMS Alpha Software" (Part II of the Alpha Architecture    "OpenVMS Alpha Software" (Part II of the Alpha Architecture
142    Manual).  This stuff should apply to Unix (OSF1) as well as VMS.    Manual).  This stuff should apply to Unix (OSF1) as well as VMS.
143    
144    
145    
146    
147    
148    
149    
150                    -------------------o*o----------------------
151                               LIVE/KILL instructions
152                                     Nov 28, 2001
153                                      Lal George
154    
155      The mechanism described above is now obsolete. We no longer use
156      the DEFFREG instruction but the zero length LIVE instruction.
157      Therefore the code that gets generated is something like;
158    
159            f1 := f2 + f3
160            trap
161            LIVE f1, f2, f3
162    
163      The live ranges for f1, f2, and f3 are extended by the LIVE
164      instruction, and are live simultaneously and therefore cannot
165      be allocated to the same register.
166    
167      Multiple floating point instructions should be surrounded
168      by parallel copies. That is to say, if we have:
169    
170            f1 := f2 + f3
171            trapb
172            LIVE f1, f2, f3
173    
174            f4 := f1 * f2
175            trapb
176            LIVE f1, f2, f4
177    
178      Then the sequence above should be transformed to:
179    
180            [f2', f3'] := [f1, f2] ; parallel copy
181            f1' := f2' + f3'
182            f4' := f1' * f2'
183            trapb
184            LIVE f1', f2', f3', f4'
185            [f4] := [f4']  ; copy assuming f4 is the only value live.
186    
187      The parallel copies are to ensure that the primed variables will
188      not spill, and there should never be more than K reigsters in the LIVE
189      instruction (K is the number of registers on the machine).
190    ****************************************************************)    ****************************************************************)
191    
192    fun error msg = MLRiscErrorMsg.error("Alpha",msg)    fun error msg = MLRiscErrorMsg.error("Alpha",msg)
193    
194    type instrStream = (I.instruction,C.cellset) T.stream    type instrStream = (I.instruction, C.cellset, CFG.cfg) TS.stream
195    type mltreeStream = (T.stm,T.mlrisc list) T.stream    type mltreeStream = (T.stm, T.mlrisc list, CFG.cfg) TS.stream
196    
197    (*    (*
198     * This module is used to simulate operations of non-standard widths.     * This module is used to simulate operations of non-standard widths.
# Line 169  Line 219 
219    functor Multiply32 = MLTreeMult    functor Multiply32 = MLTreeMult
220      (structure I = I      (structure I = I
221       structure T = T       structure T = T
222         structure CB = CellsBasis
223    
224       val intTy = 32       val intTy = 32
225    
226       type arg  = {r1:C.cell,r2:C.cell,d:C.cell}       type arg  = {r1:CB.cell,r2:CB.cell,d:CB.cell}
227       type argi = {r:C.cell,i:int,d:C.cell}       type argi = {r:CB.cell,i:int,d:CB.cell}
228    
229       fun mov{r,d}    = I.COPY{dst=[d],src=[r],tmp=NONE,impl=ref NONE}       fun mov{r,d}    = I.COPY{k=CB.GP, sz=intTy, dst=[d],src=[r],tmp=NONE}
230       fun add{r1,r2,d} = I.OPERATE{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}       fun add{r1,r2,d} = I.operate{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}
231       (*       (*
232        * How to left shift by a constant (32bits)        * How to left shift by a constant (32bits)
233        *)        *)
234       fun slli{r,i=1,d} = [I.OPERATE{oper=I.ADDL,ra=r,rb=I.REGop r,rc=d}]       fun slli{r,i=1,d} = [I.operate{oper=I.ADDL,ra=r,rb=I.REGop r,rc=d}]
235         | slli{r,i=2,d} = [I.OPERATE{oper=I.S4ADDL,ra=r,rb=zeroOpn,rc=d}]         | slli{r,i=2,d} = [I.operate{oper=I.S4ADDL,ra=r,rb=zeroOpn,rc=d}]
236         | slli{r,i=3,d} = [I.OPERATE{oper=I.S8ADDL,ra=r,rb=zeroOpn,rc=d}]         | slli{r,i=3,d} = [I.operate{oper=I.S8ADDL,ra=r,rb=zeroOpn,rc=d}]
237         | slli{r,i,d}   =         | slli{r,i,d}   =
238            let val tmp = C.newReg()            let val tmp = C.newReg()
239            in  [I.OPERATE{oper=I.SLL,ra=r,rb=I.IMMop i,rc=tmp},            in  [I.operate{oper=I.SLL,ra=r,rb=I.IMMop i,rc=tmp},
240                 I.OPERATE{oper=I.ADDL,ra=tmp,rb=zeroOpn,rc=d}]                 I.operate{oper=I.ADDL,ra=tmp,rb=zeroOpn,rc=d}]
241            end            end
242    
243       (*       (*
# Line 194  Line 245 
245        *)        *)
246       fun srli{r,i,d} =       fun srli{r,i,d} =
247           let val tmp = C.newReg()           let val tmp = C.newReg()
248           in  [I.OPERATE{oper=I.ZAP,ra=r,rb=I.IMMop 0xf0,rc=tmp},           in  [I.operate{oper=I.ZAP,ra=r,rb=I.IMMop 0xf0,rc=tmp},
249                I.OPERATE{oper=I.SRL,ra=tmp,rb=I.IMMop i,rc=d}]                I.operate{oper=I.SRL,ra=tmp,rb=I.IMMop i,rc=d}]
250           end           end
251    
252       (*       (*
# Line 203  Line 254 
254        *)        *)
255       fun srai{r,i,d} =       fun srai{r,i,d} =
256           let val tmp = C.newReg()           let val tmp = C.newReg()
257           in  [I.OPERATE{oper=I.ADDL,ra=r,rb=zeroOpn,rc=tmp},           in  [I.operate{oper=I.ADDL,ra=r,rb=zeroOpn,rc=tmp},
258                I.OPERATE{oper=I.SRA,ra=tmp,rb=I.IMMop i,rc=d}]                I.operate{oper=I.SRA,ra=tmp,rb=I.IMMop i,rc=d}]
259           end           end
260      )      )
261    
262    functor Multiply64 = MLTreeMult    functor Multiply64 = MLTreeMult
263      (structure I = I      (structure I = I
264       structure T = T       structure T = T
265         structure CB = CellsBasis
266    
267       val intTy = 64       val intTy = 64
268    
269       type arg  = {r1:C.cell,r2:C.cell,d:C.cell}       type arg  = {r1:CB.cell, r2:CB.cell, d:CB.cell}
270       type argi = {r:C.cell,i:int,d:C.cell}       type argi = {r:CB.cell, i:int, d:CB.cell}
271    
272       fun mov{r,d}    = I.COPY{dst=[d],src=[r],tmp=NONE,impl=ref NONE}       fun mov{r,d}    = I.COPY{k=CB.GP, sz=intTy, dst=[d],src=[r],tmp=NONE}
273       fun add{r1,r2,d}= I.OPERATE{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}       fun add{r1,r2,d}= I.operate{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}
274       fun slli{r,i,d} = [I.OPERATE{oper=I.SLL,ra=r,rb=I.IMMop i,rc=d}]       fun slli{r,i,d} = [I.operate{oper=I.SLL,ra=r,rb=I.IMMop i,rc=d}]
275       fun srli{r,i,d} = [I.OPERATE{oper=I.SRL,ra=r,rb=I.IMMop i,rc=d}]       fun srli{r,i,d} = [I.operate{oper=I.SRL,ra=r,rb=I.IMMop i,rc=d}]
276       fun srai{r,i,d} = [I.OPERATE{oper=I.SRA,ra=r,rb=I.IMMop i,rc=d}]       fun srai{r,i,d} = [I.operate{oper=I.SRA,ra=r,rb=I.IMMop i,rc=d}]
277      )      )
278    
279    (* signed, trapping version of multiply and divide *)    (* signed, trapping version of multiply and divide *)
280    structure Mult32 = Multiply32    structure Mult32 = Multiply32
281      (val trapping = true      (val trapping = true
282       val multCost = multCost       val multCost = multCost
283       fun addv{r1,r2,d} = [I.OPERATEV{oper=I.ADDLV,ra=r1,rb=I.REGop r2,rc=d}]       fun addv{r1,r2,d} = [I.operatev{oper=I.ADDLV,ra=r1,rb=I.REGop r2,rc=d}]
284       fun subv{r1,r2,d} = [I.OPERATEV{oper=I.SUBLV,ra=r1,rb=I.REGop r2,rc=d}]       fun subv{r1,r2,d} = [I.operatev{oper=I.SUBLV,ra=r1,rb=I.REGop r2,rc=d}]
285       val sh1addv = NONE       val sh1addv = NONE
286       val sh2addv = NONE       val sh2addv = NONE
287       val sh3addv = NONE       val sh3addv = NONE
# Line 240  Line 292 
292    functor Mul32 = Multiply32    functor Mul32 = Multiply32
293      (val trapping = false      (val trapping = false
294       val multCost = multCost       val multCost = multCost
295       fun addv{r1,r2,d} = [I.OPERATE{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}]       fun addv{r1,r2,d} = [I.operate{oper=I.ADDL,ra=r1,rb=I.REGop r2,rc=d}]
296       fun subv{r1,r2,d} = [I.OPERATE{oper=I.SUBL,ra=r1,rb=I.REGop r2,rc=d}]       fun subv{r1,r2,d} = [I.operate{oper=I.SUBL,ra=r1,rb=I.REGop r2,rc=d}]
297       val sh1addv = NONE       val sh1addv = NONE
298       val sh2addv = SOME(fn {r1,r2,d} =>       val sh2addv = SOME(fn {r1,r2,d} =>
299                      [I.OPERATE{oper=I.S4ADDL,ra=r1,rb=I.REGop r2,rc=d}])                      [I.operate{oper=I.S4ADDL,ra=r1,rb=I.REGop r2,rc=d}])
300       val sh3addv = SOME(fn {r1,r2,d} =>       val sh3addv = SOME(fn {r1,r2,d} =>
301                      [I.OPERATE{oper=I.S8ADDL,ra=r1,rb=I.REGop r2,rc=d}])                      [I.operate{oper=I.S8ADDL,ra=r1,rb=I.REGop r2,rc=d}])
302      )      )
303    structure Mulu32 = Mul32(val signed = false)    structure Mulu32 = Mul32(val signed = false)
304    structure Muls32 = Mul32(val signed = true)    structure Muls32 = Mul32(val signed = true)
# Line 255  Line 307 
307    structure Mult64 = Multiply64    structure Mult64 = Multiply64
308      (val trapping = true      (val trapping = true
309       val multCost = multCost       val multCost = multCost
310       fun addv{r1,r2,d} = [I.OPERATEV{oper=I.ADDQV,ra=r1,rb=I.REGop r2,rc=d}]       fun addv{r1,r2,d} = [I.operatev{oper=I.ADDQV,ra=r1,rb=I.REGop r2,rc=d}]
311       fun subv{r1,r2,d} = [I.OPERATEV{oper=I.SUBQV,ra=r1,rb=I.REGop r2,rc=d}]       fun subv{r1,r2,d} = [I.operatev{oper=I.SUBQV,ra=r1,rb=I.REGop r2,rc=d}]
312       val sh1addv = NONE       val sh1addv = NONE
313       val sh2addv = NONE       val sh2addv = NONE
314       val sh3addv = NONE       val sh3addv = NONE
# Line 267  Line 319 
319    functor Mul64 = Multiply64    functor Mul64 = Multiply64
320      (val trapping = false      (val trapping = false
321       val multCost = multCost       val multCost = multCost
322       fun addv{r1,r2,d} = [I.OPERATE{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}]       fun addv{r1,r2,d} = [I.operate{oper=I.ADDQ,ra=r1,rb=I.REGop r2,rc=d}]
323       fun subv{r1,r2,d} = [I.OPERATE{oper=I.SUBQ,ra=r1,rb=I.REGop r2,rc=d}]       fun subv{r1,r2,d} = [I.operate{oper=I.SUBQ,ra=r1,rb=I.REGop r2,rc=d}]
324       val sh1addv = NONE       val sh1addv = NONE
325       val sh2addv = SOME(fn {r1,r2,d} =>       val sh2addv = SOME(fn {r1,r2,d} =>
326                      [I.OPERATE{oper=I.S4ADDQ,ra=r1,rb=I.REGop r2,rc=d}])                      [I.operate{oper=I.S4ADDQ,ra=r1,rb=I.REGop r2,rc=d}])
327       val sh3addv = SOME(fn {r1,r2,d} =>       val sh3addv = SOME(fn {r1,r2,d} =>
328                      [I.OPERATE{oper=I.S8ADDQ,ra=r1,rb=I.REGop r2,rc=d}])                      [I.operate{oper=I.S8ADDQ,ra=r1,rb=I.REGop r2,rc=d}])
329      )      )
330    structure Mulu64 = Mul64(val signed = false)    structure Mulu64 = Mul64(val signed = false)
331    structure Muls64 = Mul64(val signed = true)    structure Muls64 = Mul64(val signed = true)
# Line 289  Line 341 
341    val zeroFR = C.f31    val zeroFR = C.f31
342    val zeroEA = I.Direct zeroR    val zeroEA = I.Direct zeroR
343    val zeroT  = T.LI int_0    val zeroT  = T.LI int_0
344    val trapb = [I.TRAPB]    val trapb = [I.trapb]
345    val zeroImm = I.IMMop 0    val zeroImm = I.IMMop 0
346    
347    fun selectInstructions    fun selectInstructions
348          (instrStream as          (instrStream as
349           S.STREAM{emit,beginCluster,endCluster,           TS.S.STREAM{emit=emitInstruction,beginCluster,endCluster,getAnnotations,
350                    defineLabel,entryLabel,pseudoOp,annotation,                    defineLabel,entryLabel,pseudoOp,annotation,
351                    exitBlock,comment,...}) =                    exitBlock,comment,...}) =
352    let    let
353    
354        infix || && << >> ~>>        infix || && << >> ~>>
355    
356        val op ||  = W32.orb        val op ||  = W32.orb
# Line 309  Line 362 
362        val itow = Word.fromInt        val itow = Word.fromInt
363        val wtoi = Word.toIntX        val wtoi = Word.toIntX
364    
365          val emit = emitInstruction o I.INSTR
366    
367        val newReg = C.newReg        val newReg = C.newReg
368        val newFreg = C.newFreg        val newFreg = C.newFreg
369    
# Line 329  Line 384 
384        val (ADDSX,SUBSX,MULSX,DIVSX) =        val (ADDSX,SUBSX,MULSX,DIVSX) =
385              (I.ADDSSUD,I.SUBSSUD,I.MULSSUD,I.DIVSSUD)              (I.ADDSSUD,I.SUBSSUD,I.MULSSUD,I.DIVSSUD)
386    
387        fun mark'(i,[]) = i        fun annotate(i, an) = List.foldl (fn (a, i) => I.ANNOTATION{i=i,a=a}) i an
388          | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)        fun mark'(i, an) = emitInstruction(annotate(i,an))
389        fun mark(i,an) = emit(mark'(i,an))        fun mark(i,an) = emitInstruction(annotate(I.INSTR i,an))
390    
391        (* Fit within 16 bits? *)        (* Fit within 16 bits? *)
392        fun literal16 n = ~32768 <= n andalso n < 32768        fun literal16 n = ~32768 <= n andalso n < 32768
# Line 402  Line 457 
457    
458        (* emit a copy *)        (* emit a copy *)
459        and copy(dst,src,an) =        and copy(dst,src,an) =
460            mark(I.COPY{dst=dst,src=src,impl=ref NONE,            mark'(I.COPY{k=CB.GP, sz=32, dst=dst,src=src,
461                        tmp=case dst of                        tmp=case dst of
462                             [_] => NONE | _ => SOME(I.Direct(newReg()))},an)                             [_] => NONE | _ => SOME(I.Direct(newReg()))},an)
463    
464        (* emit a floating point copy *)        (* emit a floating point copy *)
465        and fcopy(dst,src,an) =        and fcopy(dst,src,an) =
466            mark(I.FCOPY{dst=dst,src=src,impl=ref NONE,            mark'(I.COPY{k=CB.FP, sz=64, dst=dst,src=src,
467                        tmp=case dst of                        tmp=case dst of
468                             [_] => NONE | _ => SOME(I.FDirect(newFreg()))},an)                             [_] => NONE | _ => SOME(I.FDirect(newFreg()))},an)
469    
470        and move(s,d,an) =        and move(s,d,an) =
471            if C.sameCell(s,d) orelse C.sameCell(d,zeroR) then () else            if CB.sameCell(s,d) orelse CB.sameCell(d,zeroR) then () else
472            mark(I.COPY{dst=[d],src=[s],impl=ref NONE,tmp=NONE},an)            mark'(I.COPY{k=CB.GP, sz=32, dst=[d],src=[s],tmp=NONE},an)
473    
474        and fmove(s,d,an) =        and fmove(s,d,an) =
475            if C.sameCell(s,d) orelse C.sameCell(d,zeroFR) then () else            if CB.sameCell(s,d) orelse CB.sameCell(d,zeroFR) then () else
476            mark(I.FCOPY{dst=[d],src=[s],impl=ref NONE,tmp=NONE},an)            mark'(I.COPY{k=CB.FP, sz=64, dst=[d],src=[s],tmp=NONE},an)
477    
478         (* emit an sign extension op *)         (* emit an sign extension op *)
479        and signExt32(r,d) =        and signExt32(r,d) =
# Line 468  Line 523 
523                I.IMMop(toInt(n))                I.IMMop(toInt(n))
524              else let val tmpR = newReg()              else let val tmpR = newReg()
525                   in  loadImmed(n,zeroR,tmpR,[]); I.REGop tmpR end                   in  loadImmed(n,zeroR,tmpR,[]); I.REGop tmpR end
526          | opn(e as (T.CONST _ | T.LABEL _)) = I.LABop e          | opn(e as T.CONST _) = I.LABop e
527          | opn(T.LABEXP x) = I.LABop x          | opn(T.LABEXP x) = I.LABop x
528          | opn e = I.REGop(expr e)          | opn e = I.REGop(expr e)
529    
# Line 661  Line 716 
716            | SOME 0w3 => arith(I.S8ADDQ,a,zeroT,d,an)            | SOME 0w3 => arith(I.S8ADDQ,a,zeroT,d,an)
717            | _        => arith(I.SLL,a,b,d,an)            | _        => arith(I.SLL,a,b,d,an)
718    
719        and sra32(a,b,d,an) =         (* On the alpha, all 32 bit values are already sign extended.
720            let val ra = expr a          * So no sign extension is necessary.  We do the same for
721                val rb = opn b          * sra32 and sra64
               val t  = newReg()  
           in  (* On the alpha, all 32 bit values are already sign extended.  
                * So no sign extension is necessary.  
                * signExt32(ra,t);  
                * mark(I.OPERATE{oper=I.SRA,ra=t,rb=rb,rc=d},an)  
722                 *)                 *)
723                mark(I.OPERATE{oper=I.SRA,ra=ra,rb=rb,rc=d},an)        and sra(a,b,d,an) =
           end  
   
       and sra64(a,b,d,an) =  
724            mark(I.OPERATE{oper=I.SRA,ra=expr a,rb=opn b,rc=d},an)            mark(I.OPERATE{oper=I.SRA,ra=expr a,rb=opn b,rc=d},an)
725    
726        and srl32(a,b,d,an) =        and srl32(a,b,d,an) =
# Line 698  Line 745 
745                    (i,I.REGop r) => gen{ra=r,rb=i,rc=rd}                    (i,I.REGop r) => gen{ra=r,rb=i,rc=rd}
746                  | (I.REGop r,i) => gen{ra=r,rb=i,rc=rd}                  | (I.REGop r,i) => gen{ra=r,rb=i,rc=rd}
747                  | (r,i)         => gen{ra=reduceOpn r,rb=i,rc=rd}                  | (r,i)         => gen{ra=reduceOpn r,rb=i,rc=rd}
748                in mark'(instr,an)::trapb end                in annotate(instr,an)::trapb end
749                fun const(e,i) =                fun const(e,i) =
750                    let val r = expr e                    let val r = expr e
751                    in  if !useMultByConst andalso                    in  if !useMultByConst andalso
752                             IntInf.>=(i, T.I.int_0) andalso                             IntInf.>=(i, T.I.int_0) andalso
753                             IntInf.<(i, T.I.int_0x100) then                             IntInf.<(i, T.I.int_0x100) then
754                           mark'(gen{ra=r,rb=I.IMMop(toInt i),rc=rd},an)::trapb                           annotate(gen{ra=r,rb=I.IMMop(toInt i),rc=rd},an)::trapb
755                        else                        else
756                           (genConst{r=r,i=toInt i,d=rd}@trapb                           (genConst{r=r,i=toInt i,d=rd}@trapb
757                            handle _ => nonconst(T.REG(ty,r),T.LI i))                            handle _ => nonconst(T.REG(ty,r),T.LI i))
# Line 714  Line 761 
761                  of (_, T.LI i) => const(e1, i)                  of (_, T.LI i) => const(e1, i)
762                   | (T.LI i, _) => const(e2, i)                   | (T.LI i, _) => const(e2, i)
763                   | _ => nonconst(e1, e2)                   | _ => nonconst(e1, e2)
764            in  app emit instrs            in  app emitInstruction instrs
765            end            end
766    
767            (* Round r towards zero.            (* Round r towards zero.
# Line 750  Line 797 
797                    case e2 of                    case e2 of
798                       T.LI i   => const(e1,i)                       T.LI i   => const(e1,i)
799                     | _        => nonconst(e1,e2)                     | _        => nonconst(e1,e2)
800            in  app emit instrs            in  app emitInstruction instrs
801            end            end
802    
803    
# Line 802  Line 849 
849    
850        (* generate pseudo instruction *)        (* generate pseudo instruction *)
851        and pseudo(instr,e1,e2,rc) =        and pseudo(instr,e1,e2,rc) =
852             app emit (instr({ra=expr e1,rb=opn e2,rc=rc}, reduceOpn))             app emitInstruction (instr({ra=expr e1,rb=opn e2,rc=rc}, reduceOpn))
853    
854        (* generate a load *)        (* generate a load *)
855        and load(ldOp,ea,d,mem,an) =        and load(ldOp,ea,d,mem,an) =
# Line 891  Line 938 
938    
939        (* generate conversion from floating point to integer *)        (* generate conversion from floating point to integer *)
940        and cvtf2i(pseudo,rounding,e,rd,an) =        and cvtf2i(pseudo,rounding,e,rd,an) =
941            app emit (pseudo{mode=rounding, fs=fexpr e, rd=rd})            app emitInstruction (pseudo{mode=rounding, fs=fexpr e, rd=rd})
942    
943        (* generate an expression and return the register that holds the result *)        (* generate an expression and return the register that holds the result *)
944        and expr(e) = let        and expr(e) = let
# Line 948  Line 995 
995            | T.SUBT(32,a,b) => arithTrap(I.SUBLV,a,b,d,an)            | T.SUBT(32,a,b) => arithTrap(I.SUBLV,a,b,d,an)
996            | T.MULT(32,a,b) =>            | T.MULT(32,a,b) =>
997                 multiply(32,                 multiply(32,
998                   fn{ra,rb,rc} => I.OPERATEV{oper=I.MULLV,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operatev{oper=I.MULLV,ra=ra,rb=rb,rc=rc},
999                   Mult32.multiply,a,b,d,trapb,an)                   Mult32.multiply,a,b,d,trapb,an)
1000            | T.MULU(32,a,b) =>            | T.MULU(32,a,b) =>
1001                 multiply(32,                 multiply(32,
1002                   fn{ra,rb,rc} => I.OPERATE{oper=I.MULL,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operate{oper=I.MULL,ra=ra,rb=rb,rc=rc},
1003                   Mulu32.multiply,a,b,d,[],an)                   Mulu32.multiply,a,b,d,[],an)
1004            | T.MULS(32,a,b) =>            | T.MULS(32,a,b) =>
1005                 multiply(32,                 multiply(32,
1006                   fn{ra,rb,rc} => I.OPERATE{oper=I.MULL,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operate{oper=I.MULL,ra=ra,rb=rb,rc=rc},
1007                   Muls32.multiply,a,b,d,[],an)                   Muls32.multiply,a,b,d,[],an)
1008            | T.DIVT(32,a,b) => divide(32,P.divlv,Mult32.divide,a,b,d,an)            | T.DIVT(32,a,b) => divide(32,P.divlv,Mult32.divide,a,b,d,an)
1009            | T.DIVU(32,a,b) => divide(32,P.divlu,Mulu32.divide,a,b,d,an)            | T.DIVU(32,a,b) => divide(32,P.divlu,Mulu32.divide,a,b,d,an)
# Line 966  Line 1013 
1013            | T.REMS(32,a,b) => pseudo(P.reml,a,b,d)            | T.REMS(32,a,b) => pseudo(P.reml,a,b,d)
1014    
1015            | T.SLL(32,a,b) => sll32(a,b,d,an)            | T.SLL(32,a,b) => sll32(a,b,d,an)
1016            | T.SRA(32,a,b) => sra32(a,b,d,an)            | T.SRA(32,a,b) => sra(a,b,d,an)
1017            | T.SRL(32,a,b) => srl32(a,b,d,an)            | T.SRL(32,a,b) => srl32(a,b,d,an)
1018    
1019              (* 64 bit support *)              (* 64 bit support *)
# Line 976  Line 1023 
1023            | T.SUBT(64,a,b) => arithTrap(I.SUBQV,a,b,d,an)            | T.SUBT(64,a,b) => arithTrap(I.SUBQV,a,b,d,an)
1024            | T.MULT(64,a,b) =>            | T.MULT(64,a,b) =>
1025                 multiply(64,                 multiply(64,
1026                   fn{ra,rb,rc} => I.OPERATEV{oper=I.MULQV,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operatev{oper=I.MULQV,ra=ra,rb=rb,rc=rc},
1027                   Mult64.multiply,a,b,d,trapb,an)                   Mult64.multiply,a,b,d,trapb,an)
1028            | T.MULU(64,a,b) =>            | T.MULU(64,a,b) =>
1029                 multiply(64,                 multiply(64,
1030                   fn{ra,rb,rc} => I.OPERATE{oper=I.MULQ,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operate{oper=I.MULQ,ra=ra,rb=rb,rc=rc},
1031                   Mulu64.multiply,a,b,d,[],an)                   Mulu64.multiply,a,b,d,[],an)
1032            | T.MULS(64,a,b) =>            | T.MULS(64,a,b) =>
1033                 multiply(64,                 multiply(64,
1034                   fn{ra,rb,rc} => I.OPERATE{oper=I.MULQ,ra=ra,rb=rb,rc=rc},                   fn{ra,rb,rc} => I.operate{oper=I.MULQ,ra=ra,rb=rb,rc=rc},
1035                   Muls64.multiply,a,b,d,[],an)                   Muls64.multiply,a,b,d,[],an)
1036            | T.DIVT(64,a,b) => divide(64,P.divqv,Mult64.divide,a,b,d,an)            | T.DIVT(64,a,b) => divide(64,P.divqv,Mult64.divide,a,b,d,an)
1037            | T.DIVU(64,a,b) => divide(64,P.divqu,Mulu64.divide,a,b,d,an)            | T.DIVU(64,a,b) => divide(64,P.divqu,Mulu64.divide,a,b,d,an)
# Line 994  Line 1041 
1041            | T.REMS(64,a,b) => pseudo(P.remq,a,b,d)            | T.REMS(64,a,b) => pseudo(P.remq,a,b,d)
1042    
1043            | T.SLL(64,a,b) => sll64(a,b,d,an)            | T.SLL(64,a,b) => sll64(a,b,d,an)
1044            | T.SRA(64,a,b) => sra64(a,b,d,an)            | T.SRA(64,a,b) => sra(a,b,d,an)
1045            | T.SRL(64,a,b) => srl64(a,b,d,an)            | T.SRL(64,a,b) => srl64(a,b,d,an)
1046    
1047              (* special bit operations with complement *)              (* special bit operations with complement *)
# Line 1070  Line 1117 
1117            let val fa = fexpr a            let val fa = fexpr a
1118                val fb = fexpr b                val fb = fexpr b
1119            in  if SMLNJfloatingPoint then            in  if SMLNJfloatingPoint then
1120                     (emit(I.DEFFREG d);                     ((* emit(I.DEFFREG d); *)
1121                      mark(I.FOPERATEV{oper=opcodeSMLNJ,fa=fa,fb=fb,fc=d},an);                      mark(I.FOPERATEV{oper=opcodeSMLNJ,fa=fa,fb=fb,fc=d},an);
1122                      emit(I.TRAPB)                      emit(I.TRAPB);
1123                        emitInstruction(I.LIVE{regs=List.foldl C.addFreg C.empty [fa,fb,d],
1124                                               spilled=[]})
1125    
1126                     )                     )
1127                else mark(I.FOPERATE{oper=opcode,fa=fa,fb=fb,fc=d},an)                else mark(I.FOPERATE{oper=opcode,fa=fa,fb=fb,fc=d},an)
1128            end            end
# Line 1092  Line 1142 
1142        (* generate an external floating point operation *)        (* generate an external floating point operation *)
1143        and fcvti2f(pseudo,e,fd,an) =        and fcvti2f(pseudo,e,fd,an) =
1144            let val opnd = opn e            let val opnd = opn e
1145            in  app emit (pseudo({opnd=opnd, fd=fd}, reduceOpn))            in  app emitInstruction (pseudo({opnd=opnd, fd=fd}, reduceOpn))
1146            end            end
1147    
1148        (* generate a floating point store *)        (* generate a floating point store *)
# Line 1194  Line 1244 
1244                  val f2 = fexpr e2                  val f2 = fexpr e2
1245                  fun bcc(cmp,br) =                  fun bcc(cmp,br) =
1246                  let val tmpR = C.newFreg()                  let val tmpR = C.newFreg()
1247                  in  emit(I.DEFFREG(tmpR));                  in  (*emit(I.DEFFREG(tmpR));*)
1248                      emit(I.FOPERATE{oper=cmp,fa=f1,fb=f2,fc=tmpR});                      emit(I.FOPERATE{oper=cmp,fa=f1,fb=f2,fc=tmpR});
1249                      emit(I.TRAPB);                      emit(I.TRAPB);
1250                        emitInstruction(I.LIVE{regs=List.foldl C.addFreg C.empty [f1,f2,tmpR],
1251                                    spilled=[]});
1252                      mark(I.FBRANCH{b=br,f=tmpR,lab=lab},an)                      mark(I.FBRANCH{b=br,f=tmpR,lab=lab},an)
1253                  end                  end
1254                  fun fall(cmp1, br1, cmp2, br2) =                  fun fall(cmp1, br1, cmp2, br2) =
1255                  let val tmpR1 = newFreg()                  let val tmpR1 = newFreg()
1256                      val tmpR2 = newFreg()                      val tmpR2 = newFreg()
1257                      val fallLab = Label.newLabel ""                      val fallLab = Label.anon()
1258                  in  emit(I.DEFFREG(tmpR1));                  in  (*emit(I.DEFFREG(tmpR1));*)
1259                      emit(I.FOPERATE{oper=cmp1, fa=f1, fb=f2, fc=tmpR1});                      emit(I.FOPERATE{oper=cmp1, fa=f1, fb=f2, fc=tmpR1});
1260                      emit(I.TRAPB);                      emit(I.TRAPB);
1261                        emitInstruction(I.LIVE{regs=List.foldl C.addFreg C.empty [f1,f2,tmpR1],
1262                                    spilled=[]});
1263                      mark(I.FBRANCH{b=br1, f=tmpR1, lab=fallLab},an);                      mark(I.FBRANCH{b=br1, f=tmpR1, lab=fallLab},an);
1264                      emit(I.DEFFREG(tmpR2));                      (* emit(I.DEFFREG(tmpR2)); *)
1265                      emit(I.FOPERATE{oper=cmp2, fa=f1, fb=f2, fc=tmpR2});                      emit(I.FOPERATE{oper=cmp2, fa=f1, fb=f2, fc=tmpR2});
1266                      emit(I.TRAPB);                      emit(I.TRAPB);
1267                        emitInstruction(I.LIVE{regs=List.foldl C.addFreg C.empty [f1,f2,tmpR2],
1268                                    spilled=[]});
1269                      mark(I.FBRANCH{b=br2, f=tmpR2, lab=lab},an);                      mark(I.FBRANCH{b=br2, f=tmpR2, lab=lab},an);
1270                      defineLabel fallLab                      defineLabel fallLab
1271                  end                  end
# Line 1416  Line 1472 
1472        and goto(lab,an) = mark(I.BRANCH{b=I.BR,r=zeroR,lab=lab},an)        and goto(lab,an) = mark(I.BRANCH{b=I.BR,r=zeroR,lab=lab},an)
1473    
1474           (* generate an call instruction *)           (* generate an call instruction *)
1475        and call(ea,flow,defs,uses,mem,an) =        and call(ea,flow,defs,uses,mem,cutTo,an,0) =
1476         let val defs=cellset defs         let val defs=cellset defs
1477             val uses=cellset uses             val uses=cellset uses
1478             val instr =             val instr =
1479                 case (ea, flow) of                 case (ea, flow) of
1480                   (T.LABEL lab, [_]) =>                   (T.LABEL lab, [_]) =>
1481                     I.BSR{lab=lab,r=C.returnAddr,defs=defs,uses=uses,mem=mem}                        I.BSR{lab=lab,r=C.returnAddr,defs=defs,uses=uses,
1482                                cutsTo=cutTo,mem=mem}
1483                 | _ => I.JSR{r=C.returnAddr,b=expr ea,                 | _ => I.JSR{r=C.returnAddr,b=expr ea,
1484                              d=0,defs=defs,uses=uses,mem=mem}                                   d=0,defs=defs,uses=uses,cutsTo=cutTo,mem=mem}
1485         in  mark(instr,an)         in  mark(instr,an)
1486         end         end
1487            | call _ = error "pops<>0 not implemented"
1488    
1489        and doCCexpr(T.CC(_,r),d,an) = move(r,d,an)        and doCCexpr(T.CC(_,r),d,an) = move(r,d,an)
1490          | doCCexpr(T.FCC(_,r),d,an) = fmove(r,d,an)          | doCCexpr(T.FCC(_,r),d,an) = fmove(r,d,an)
# Line 1454  Line 1512 
1512            | T.JMP(T.LABEL lab,_) => goto(lab,an)            | T.JMP(T.LABEL lab,_) => goto(lab,an)
1513            | T.JMP(e,labs) => mark(I.JMPL({r=zeroR,b=expr e,d=0},labs),an)            | T.JMP(e,labs) => mark(I.JMPL({r=zeroR,b=expr e,d=0},labs),an)
1514            | T.BCC(cc,lab) => branch(cc,lab,an)            | T.BCC(cc,lab) => branch(cc,lab,an)
1515            | T.CALL{funct,targets,defs,uses,region,...} =>            | T.CALL{funct,targets,defs,uses,region,pops,...} =>
1516                call(funct,targets,defs,uses,region,an)                call(funct,targets,defs,uses,region,[],an,pops)
1517              | T.FLOW_TO(T.CALL{funct,targets,defs,uses,region,pops,...},cutTo) =>
1518                  call(funct,targets,defs,uses,region,cutTo,an,pops)
1519            | T.RET _ => mark(I.RET{r=zeroR,b=C.returnAddr,d=0},an)            | T.RET _ => mark(I.RET{r=zeroR,b=C.returnAddr,d=0},an)
1520            | T.STORE(8,ea,data,mem) => store8(ea,data,mem,an)            | T.STORE(8,ea,data,mem) => store8(ea,data,mem,an)
1521            | T.STORE(16,ea,data,mem) => store16(ea,data,mem,an)            | T.STORE(16,ea,data,mem) => store16(ea,data,mem,an)
# Line 1466  Line 1526 
1526            | T.DEFINE l => defineLabel l            | T.DEFINE l => defineLabel l
1527            | T.ANNOTATION(s,a) => stmt(s,a::an)            | T.ANNOTATION(s,a) => stmt(s,a::an)
1528            | T.EXT s => ExtensionComp.compileSext (reducer()) {stm=s,an=an}            | T.EXT s => ExtensionComp.compileSext (reducer()) {stm=s,an=an}
1529              | T.LIVE rs => mark'(I.LIVE{regs=cellset rs, spilled=[]}, an)
1530              | T.KILL rs => mark'(I.KILL{regs=cellset rs, spilled=[]}, an)
1531            | s => doStmts (Gen.compileStm s)            | s => doStmts (Gen.compileStm s)
1532    
1533        and reducer() =        and reducer() =
1534            T.REDUCER{reduceRexp    = expr,            TS.REDUCER{reduceRexp    = expr,
1535                      reduceFexp    = fexpr,                      reduceFexp    = fexpr,
1536                      reduceCCexp   = ccExpr,                      reduceCCexp   = ccExpr,
1537                      reduceStm     = stmt,                      reduceStm     = stmt,
1538                      operand       = opn,                      operand       = opn,
1539                      reduceOperand = reduceOpn,                      reduceOperand = reduceOpn,
1540                      addressOf     = addr,                      addressOf     = addr,
1541                      emit          = mark,                       emit          = emitInstruction o annotate,
1542                      instrStream   = instrStream,                      instrStream   = instrStream,
1543                      mltreeStream  = self()                      mltreeStream  = self()
1544                     }                     }
# Line 1497  Line 1559 
1559            in  g(mlrisc, C.empty) end            in  g(mlrisc, C.empty) end
1560    
1561        and self() =        and self() =
1562            S.STREAM            TS.S.STREAM
1563           { beginCluster= beginCluster,           { beginCluster= beginCluster,
1564             endCluster  = endCluster,             endCluster  = endCluster,
1565             emit        = doStmt,             emit        = doStmt,
# Line 1506  Line 1568 
1568             entryLabel  = entryLabel,             entryLabel  = entryLabel,
1569             comment     = comment,             comment     = comment,
1570             annotation  = annotation,             annotation  = annotation,
1571               getAnnotations = getAnnotations,
1572             exitBlock   = fn regs => exitBlock(cellset regs)             exitBlock   = fn regs => exitBlock(cellset regs)
1573           }           }
1574     in  self()     in  self()

Legend:
Removed from v.788  
changed lines
  Added in v.1009

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0