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[smlnj] Diff of /sml/trunk/src/MLRISC/alpha/mltree/alphaPseudoInstr.sig
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Diff of /sml/trunk/src/MLRISC/alpha/mltree/alphaPseudoInstr.sig

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revision 888, Thu Jul 19 20:24:21 2001 UTC revision 889, Thu Jul 19 20:35:20 2001 UTC
# Line 7  Line 7 
7     structure C : ALPHACELLS     structure C : ALPHACELLS
8       sharing C = I.C       sharing C = I.C
9       sharing I.T = T       sharing I.T = T
10       structure CB: CELLS_BASIS = CellsBasis
11    
12     type reduceOpnd = I.operand -> C.cell     type reduceOpnd = I.operand -> CB.cell
13    
14     val divlv : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val divlv : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
15     val divl  : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val divl  : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
16     val divlu : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val divlu : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
17     val remlv : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val remlv : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
18     val reml  : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val reml  : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
19     val remlu : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val remlu : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
20     val divqv : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val divqv : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
21     val divq  : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val divq  : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
22     val divqu : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val divqu : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
23     val remqv : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val remqv : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
24     val remq  : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val remq  : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
25     val remqu : {ra:C.cell, rb:I.operand, rc:C.cell} * reduceOpnd -> I.instruction list     val remqu : {ra:CB.cell, rb:I.operand, rc:CB.cell} * reduceOpnd -> I.instruction list
26    
27     val cvtls : {opnd:I.operand, fd:C.cell} * reduceOpnd -> I.instruction list     val cvtls : {opnd:I.operand, fd:CB.cell} * reduceOpnd -> I.instruction list
28     val cvtlt : {opnd:I.operand, fd:C.cell} * reduceOpnd -> I.instruction list     val cvtlt : {opnd:I.operand, fd:CB.cell} * reduceOpnd -> I.instruction list
29     val cvtqs : {opnd:I.operand, fd:C.cell} * reduceOpnd -> I.instruction list     val cvtqs : {opnd:I.operand, fd:CB.cell} * reduceOpnd -> I.instruction list
30     val cvtqt : {opnd:I.operand, fd:C.cell} * reduceOpnd -> I.instruction list     val cvtqt : {opnd:I.operand, fd:CB.cell} * reduceOpnd -> I.instruction list
31    
32     val cvtsl : {mode:T.rounding_mode, fs:C.cell, rd:C.cell} -> I.instruction list     val cvtsl : {mode:T.rounding_mode, fs:CB.cell, rd:CB.cell} -> I.instruction list
33     val cvttl : {mode:T.rounding_mode, fs:C.cell, rd:C.cell} -> I.instruction list     val cvttl : {mode:T.rounding_mode, fs:CB.cell, rd:CB.cell} -> I.instruction list
34     val cvtsq : {mode:T.rounding_mode, fs:C.cell, rd:C.cell} -> I.instruction list     val cvtsq : {mode:T.rounding_mode, fs:CB.cell, rd:CB.cell} -> I.instruction list
35     val cvttq : {mode:T.rounding_mode, fs:C.cell, rd:C.cell} -> I.instruction list     val cvttq : {mode:T.rounding_mode, fs:CB.cell, rd:CB.cell} -> I.instruction list
36  end  end
37    

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