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[smlnj] Annotation of /sml/trunk/src/MLRISC/alpha32/alpha32RegAlloc.sml
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Annotation of /sml/trunk/src/MLRISC/alpha32/alpha32RegAlloc.sml

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1 : monnier 16 (* alpha32RegAlloc.sml --- alpha integer and floating register allocator
2 :     *
3 :     * COPYRIGHT (c) 1996 AT&T Bell Laboratories.
4 :     *
5 :     *)
6 :    
7 :     (* Integer and floating register allocators are a partial application
8 :     * of a curried functor.
9 :     *)
10 :    
11 :    
12 :    
13 :     functor Alpha32RegAlloc(structure P : INSN_PROPERTIES
14 :     structure F : FLOWGRAPH
15 :     structure I : INSTRUCTIONS where C = Alpha32Cells
16 :     structure Asm : EMITTER_NEW
17 :     sharing Asm.F = F
18 :     sharing P.I = F.I = Asm.I = I) :
19 :     sig
20 :     functor IntRa (structure RaUser : RA_USER_PARAMS
21 :     where type I.operand = I.operand
22 :     and type I.instruction = I.instruction
23 : monnier 127 and type B.name = F.B.name
24 : monnier 16 (* should be: where I = I -- bug 1205 *)) : sig
25 :     datatype mode = REGISTER_ALLOCATION | COPY_PROPAGATION
26 :     val ra : mode -> F.cluster -> F.cluster
27 :     end
28 :     functor FloatRa (structure RaUser : RA_USER_PARAMS
29 :     where type I.operand = I.operand
30 :     and type I.instruction = I.instruction
31 : monnier 127 and type B.name = F.B.name
32 : monnier 16 (* should be: where I = I *)) : sig
33 :     datatype mode = REGISTER_ALLOCATION | COPY_PROPAGATION
34 :     val ra : mode -> F.cluster -> F.cluster
35 :     end
36 :     end =
37 :     struct
38 : monnier 106 structure C = I.C
39 : monnier 16 (* liveness analysis for general purpose registers *)
40 :     structure RegLiveness =
41 :     Liveness(structure Flowgraph=F
42 :     structure Instruction=I
43 : monnier 106 val defUse = P.defUse C.GP
44 : monnier 16 fun regSet c = #1 (c:Alpha32Cells.cellset)
45 :     fun cellset((_,f),r) = (r,f))
46 :    
47 :    
48 :     (* integer register allocator *)
49 :     functor IntRa =
50 :     RegAllocator
51 :     (structure RaArch = struct
52 :    
53 :     structure InsnProps = P
54 :     structure AsmEmitter = Asm
55 :     structure I = I
56 :     structure Liveness=RegLiveness
57 : monnier 106 val defUse = P.defUse C.GP
58 : monnier 16 val firstPseudoR = 32
59 : monnier 106 val maxPseudoR = Alpha32Cells.maxCell
60 :     val numRegs = Alpha32Cells.numCell Alpha32Cells.GP
61 : monnier 16 fun regSet c = #1 (c:Alpha32Cells.cellset)
62 :     end)
63 :    
64 :    
65 :    
66 :     (* liveness analysis for floating point registers *)
67 :     structure FregLiveness =
68 :     Liveness(structure Flowgraph=F
69 :     structure Instruction=I
70 : monnier 106 val defUse = P.defUse C.FP
71 : monnier 16 fun regSet c = #2 (c:Alpha32Cells.cellset)
72 :     fun cellset((r,_),f) = (r,f))
73 :    
74 :     (* floating register allocator *)
75 :     functor FloatRa =
76 :     RegAllocator
77 :     (structure RaArch = struct
78 :    
79 :     structure InsnProps = P
80 :     structure AsmEmitter = Asm
81 :     structure Liveness=FregLiveness
82 :     structure I = I
83 :    
84 : monnier 106 val defUse = P.defUse C.FP
85 : monnier 16 val firstPseudoR = 32
86 : monnier 106 val maxPseudoR = Alpha32Cells.maxCell
87 :     val numRegs = Alpha32Cells.numCell Alpha32Cells.FP
88 : monnier 16 fun regSet c = #2 (c:Alpha32Cells.cellset)
89 :     end)
90 :     end
91 :    
92 :    
93 :    
94 :    

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