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View of /sml/trunk/src/MLRISC/cm/MLRISC.cm

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Revision 1003 - (download) (annotate)
Fri Dec 7 02:45:32 2001 UTC (18 years, 1 month ago) by george
File size: 6284 byte(s)
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.
(* This file is created by makeallcm *)
Library
	signature ASM_FORMAT_UTIL
	signature ASM_STREAM
	signature ASSEMBLY_EMITTER
	signature BBSCHED
	signature BLOCK_PLACEMENT
	signature CELLS
	signature CELLS_BASIS
	signature CFG_OPTIMIZATION
	signature CFG_VIEW
	signature CLIENT_PSEUDO_OPS
	signature CODE_STRING
	signature CONSTANT
	signature CONTROL_FLOWGRAPH_GEN
	signature CONTROL_FLOW_GRAPH
	signature C_CALLS
	signature DELAY_SLOT_PROPERTIES
	signature EXPAND_COPIES
	signature FREQUENCY_PROPERTIES
	signature GAS_PSEUDO_OPS
	signature GC_CELLS
	signature GC_TYPE
	signature GETREG
	signature INSN_PROPERTIES
	signature INSTRUCTIONS
	signature INSTRUCTION_EMITTER
	signature INSTRUCTION_STREAM
	signature LABEL
	signature LIVENESS
	signature MACHINE_INT
	signature MC_EMIT
	signature MLRISC_ANNOTATIONS
	signature MLRISC_OPTIMIZATION
	signature MLRISC_REGION
	signature MLTREE
	signature MLTREECOMP
	signature MLTREEGEN
	signature MLTREE_BASIS
	signature MLTREE_EVAL
	signature MLTREE_EXTENSION
	signature MLTREE_EXTENSION_COMP
	signature MLTREE_HASH
	signature MLTREE_MULT_DIV
	signature MLTREE_SIZE
	signature MLTREE_STREAM
	signature OMIT_FRAME_POINTER
	signature POINTS_TO
	signature PRINT_FLOWGRAPH
	signature PSEUDO_OPS
	signature PSEUDO_OPS_BASIS
	signature PSEUDO_OPS_ENDIAN
	signature RA
	signature RA_CORE
	signature RA_FLOWGRAPH
	signature RA_FLOWGRAPH_PARTITIONER
	signature RA_GRAPH
	signature RA_PRIORITY_QUEUE
	signature RA_SPILL
	signature RA_SPILL_HEURISTICS
	signature REGION
	signature REWRITE_INSTRUCTIONS
	signature SDI_JUMPS
	signature SHUFFLE
	structure AsmFormatUtil
	structure AsmStream
	structure CTypes
	structure CellsBasis
	structure ChaitinSpillHeur
	structure ChowHennessySpillHeur
	structure Label
	structure MLRiscAnnotations
	structure MLRiscRegion
	structure MLTreeBasis
	structure MachineInt
	structure PointsTo
	structure PseudoOpsBasisTyp
	structure RACore
	structure RAGraph
	functor BBSched2
	functor BackPatch
	functor BuildFlowgraph
	functor CFGCountCopies
	functor CFGEmit
	functor CFGExpandCopies
	functor CFGView
	functor Cells
	functor ClusterRA
	functor ControlFlowGraph
	functor DefaultBlockPlacement
	functor FreqProps
	functor GCCells
	functor GasPseudoOps
	functor GetReg
	functor GetReg2
	functor InstructionStream
	functor Liveness
	functor MLTreeEval
	functor MLTreeF
	functor MLTreeGen
	functor MLTreeHash
	functor MLTreeMult
	functor MLTreeSize
	functor MLTreeStream
	functor MemoryRA
	functor NoDelaySlots
	functor PrintFlowgraph
	functor PseudoOps
	functor PseudoOpsBig
	functor PseudoOpsLittle
	functor RADeadCodeElim
	functor RASpill
	functor RASpillTypes
	functor RISC_RA
	functor RegionBasedRA
	functor RegisterAllocator
	functor Shuffle
	functor SpanDependencyResolution
is
#if defined(NEW_CM)
#if SMLNJ_VERSION * 100 + SMLNJ_MINOR_VERSION >= 11030
	$/basis.cm
#if defined(UNSHARED_MLRISC)
	$/smlnj-lib.cm
	Control.cm
	Graphs.cm
	Visual.cm
	Lib.cm
#else
	$/smlnj-lib.cm
	$/Control.cm
	$/Graphs.cm
	$/Visual.cm
	$/Lib.cm
#endif
#else
	basis.cm
	smlnj-lib.cm
	Control.cm
	Graphs.cm
	Visual.cm
	Lib.cm
#endif
#else
	smlnj-lib.cm
	Control.cm
	Graphs.cm
	Visual.cm
	Lib.cm
#endif
	../instructions/cells.sig
	../instructions/cells.sml
	../instructions/cells-basis.sig
	../instructions/cells-basis.sml
	../instructions/expandCopies.sig
	../instructions/rewrite.sig
	../instructions/insnProps.sig
	../instructions/stream.sig
	../instructions/stream.sml
	../instructions/instructions.sig
	../instructions/shuffle.sig
	../instructions/shuffle.sml
	../instructions/constant.sig
	../instructions/label.sml
	../instructions/label-sig.sml
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	../instructions/freqProps.sml
	../instructions/mlriscAnnotations.sig
	../instructions/mlriscAnnotations.sml
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	../flowgraph/cfgView.sig
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	../flowgraph/gasPseudoOps.sml
	../flowgraph/printFlowgraph.sml
	../flowgraph/pseudo-ops.sig
	../flowgraph/pseudo-ops.sml
	../flowgraph/pseudo-ops-basis.sig
	../flowgraph/pseudo-ops-basis-typ.sml
	../flowgraph/pseudo-ops-big.sml
	../flowgraph/pseudo-ops-endian.sig
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	../ra/getreg.sig
	../ra/getreg.sml
	../ra/getreg2.sml
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        ../ra/chow-hennessy-spillheur.sml
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        ../ra/ra-graph.sml
        ../ra/ra-core.sig
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        ../ra/ra-spill.sig
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        ../ra/ra-spillheur.sig
        ../ra/ra-flowgraph.sig
        ../ra/ra-flowgraph-part.sig
        ../ra/ra.sig
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	../ra/mem-ra.sml
	../ra/region-based-ra.sml
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        ../ra/cluster-ra.sml
	../emit/instruction-emitter.sig
	../emit/asmEmit.sig 
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	../gc-safety/gc-type.sig
	../backpatch/backpatch.sml
	../backpatch/bbsched.sig
	../backpatch/spanDep.sml
	../backpatch/delaySlotProps.sig
	../backpatch/noDelaySlots.sml
	../backpatch/sdi-jumps.sig
	../backpatch/vlBackPatch.sml
	../block-placement/block-placement.sig
	../block-placement/default-block-placement.sml
        ../c-calls/c-types.sml
        ../c-calls/c-calls.sig
 	../omit-frameptr/omit-frame-pointer.sig

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