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[smlnj] Diff of /sml/trunk/src/MLRISC/demo/demo-alpha.sml
 [smlnj] / sml / trunk / src / MLRISC / demo / demo-alpha.sml

# Diff of /sml/trunk/src/MLRISC/demo/demo-alpha.sml

revision 713, Mon Oct 23 23:38:38 2000 UTC revision 744, Fri Dec 8 04:11:42 2000 UTC
# Line 43  Line 43
43    structure T = MLTree    structure T = MLTree
44    structure C = I.C    structure C = I.C
45
46    type reduceOpnd = I.operand -> int    type reduceOpnd = I.operand -> C.cell
47
48    (* reduceOpnd moves the operand to a register if it's not in one    (* reduceOpnd moves the operand to a register if it's not in one
# Line 53  Line 53
53       Sigh ...       Sigh ...
54     *)     *)
55
56    val temps = foldr C.addReg C.empty [23, 24, 25, 26, 28]    val temps = foldr C.addReg C.empty (map C.GPReg [23, 24, 25, 26, 28])
57
58    fun pseudoArith instr ({ra, rb, rc}, reduceOpnd) =    fun pseudoArith instr ({ra, rb, rc}, reduceOpnd) =
59        [I.PSEUDOARITH{oper=instr, ra=ra, rb=I.REGop(reduceOpnd rb), rc=rc, tmps=temps}]        [I.PSEUDOARITH{oper=instr, ra=ra, rb=I.REGop(reduceOpnd rb), rc=rc, tmps=temps}]
# Line 175  Line 175
175     (structure I          = AlphaInstr     (structure I          = AlphaInstr
176      structure Flowgraph  = AlphaFlowGraph      structure Flowgraph  = AlphaFlowGraph
177      structure InsnProps  = AlphaProps(AlphaInstr)      structure InsnProps  = AlphaProps(AlphaInstr)
structure Rewrite    = AlphaRewrite(AlphaInstr)
178      structure Asm        = AlphaAsm      structure Asm        = AlphaAsm
179      structure MLTreeComp = AlphaMLTreeComp      structure MLTreeComp = AlphaMLTreeComp
180
# Line 183  Line 182
182      val spill = UserRegion.spill      val spill = UserRegion.spill
183
184      (* I'm assuming only r31 and the stack pointer is dedicated *)      (* I'm assuming only r31 and the stack pointer is dedicated *)
185      fun range(from,to) = if from > to then []      structure RA =
186                           else from::range(from+1,to)        RISC_RA
187      val dedicatedRegs  = [I.C.stackptrR, I.C.GPReg 31]        (structure I          = I
188      val dedicatedFRegs = [I.C.FPReg 31]         structure C          = I.C
189      val availRegs      = SortedList.difference(         structure Flowgraph  = Flowgraph
190                              range(I.C.GPReg 0, I.C.GPReg 31),         structure Asm        = Asm
191                              SortedList.uniq dedicatedRegs)         structure Rewrite    = AlphaRewrite(AlphaInstr)
192      val availFRegs     = range(I.C.FPReg 0, I.C.FPReg 30)         structure InsnProps  = InsnProps
193           structure Spill      = RASpill(structure Asm = Asm
194                                          structure InsnProps = InsnProps)
195           structure SpillHeur  = ChaitinSpillHeur
196           structure SpillTable =
197             SpillTable
198             (val initialSpillOffset = 0 (* This is probably wrong!!!!! *)
199              val spillAreaSz = 4000
200              val architecture = "Alpha"
201             )
202
203      val initialSpillOffset = 0 (* This is probably wrong!!!!! *)         open SpillTable
val spillAreaSize = 4000
204
205      fun pure _ = false      fun pure _ = false
206
207      (* make copies *)      (* make copies *)
208      fun copyR((rds as [_], rss as [_]), _) =         structure Int =
209           struct
210              val dedicated  = [I.C.stackptrR, I.C.GPReg 31]
211              val avail  =
212                   C.SortedCells.return(
213                     C.SortedCells.difference(
214                        C.SortedCells.uniq(
215                          C.Regs C.GP {from=0, to=31, step=1}),
216                        C.SortedCells.uniq dedicated))
217
218              fun copy((rds as [_], rss as [_]), _) =
220        | copyR((rds, rss), I.COPY{tmp, ...}) =              | copy((rds, rss), I.COPY{tmp, ...}) =
222      fun copyF((fds as [_], fss as [_]), _) =            (* spill register *)
223          I.FCOPY{dst=fds, src=fss, impl=ref NONE, tmp=NONE}            fun spillInstr(_,r,loc) =
224        | copyF((fds, fss), I.FCOPY{tmp, ...}) =                [I.STORE{stOp=I.STL, b=sp, d=I.IMMop(get loc),
225          I.FCOPY{dst=fds, src=fss, impl=ref NONE, tmp=tmp}                         r=r, mem=spill}]
226
227      (* spill copy temp *)      (* spill copy temp *)
228      fun spillCopyTmp(I.COPY{tmp,dst,src,impl},loc) =            fun spillCopyTmp(_,I.COPY{tmp,dst,src,impl},loc) =
229          I.COPY{tmp=SOME(I.Displace{base=sp, disp=loc}),                I.COPY{tmp=SOME(I.Displace{base=sp, disp=get loc}),
dst=dst,src=src,impl=impl}
fun spillFcopyTmp(I.FCOPY{tmp,dst,src,impl},loc) =
I.FCOPY{tmp=SOME(I.Displace{base=sp, disp=loc}),
230                  dst=dst,src=src,impl=impl}                  dst=dst,src=src,impl=impl}
231
(* spill register *)
fun spillInstrR(r,offset) =
[I.STORE{stOp=I.STL, b=sp, d=I.IMMop offset, r=r, mem=spill}]
fun spillInstrF(r,offset) =
[I.FSTORE{stOp=I.STT, b=sp, d=I.IMMop offset, r=r, mem=spill}]

234          I.LOAD{ldOp=I.LDL, b=sp, d=I.IMMop offset, r=r, mem=spill}::rest                [I.LOAD{ldOp=I.LDL, b=sp, d=I.IMMop(get loc), r=r, mem=spill}]
236          I.FLOAD{ldOp=I.LDT, b=sp, d=I.IMMop offset, r=r, mem=spill}::rest
237           structure Float =
238           struct
239              val dedicated = [I.C.FPReg 31]
240              val avail = C.Regs C.FP {from=0, to=30, step=1}
241
242              fun copy((fds as [_], fss as [_]), _) =
243                  I.FCOPY{dst=fds, src=fss, impl=ref NONE, tmp=NONE}
244                | copy((fds, fss), I.FCOPY{tmp, ...}) =
245                  I.FCOPY{dst=fds, src=fss, impl=ref NONE, tmp=tmp}
246
247              fun spillCopyTmp(_,I.FCOPY{tmp,dst,src,impl},loc) =
248                  I.FCOPY{tmp=SOME(I.Displace{base=sp, disp=getF loc}),
249                          dst=dst,src=src,impl=impl}
250              fun spillInstr(_,r,loc) =
251                  [I.FSTORE{stOp=I.STT, b=sp, d=I.IMMop(getF loc), r=r, mem=spill}]
252