Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Log of /sml/trunk/src/MLRISC/hppa/backpatch/hppaDelaySlotProps.sml
[smlnj] / sml / trunk / src / MLRISC / hppa / backpatch / hppaDelaySlotProps.sml  
ViewVC logotype

Log of /sml/trunk/src/MLRISC/hppa/backpatch/hppaDelaySlotProps.sml

Parent Directory Parent Directory


Sticky Revision:
(Current path doesn't exist after revision 2125)

Revision 1003 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 7 02:45:32 2001 UTC (17 years, 8 months ago) by george
File length: 5603 byte(s)
Diff to previous 889
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.

Revision 889 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jul 19 20:35:20 2001 UTC (18 years, 1 month ago) by george
File length: 5269 byte(s)
Diff to previous 796
Substantial simplification in the CELLS interface

Revision 796 - (view) (download) (annotate) - [select for diffs]
Modified Tue Mar 6 00:04:33 2001 UTC (18 years, 5 months ago) by leunga
File length: 5237 byte(s)
Diff to previous 744

   Support for alternative control-flow, exception handlers added.

Revision 744 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 8 04:11:42 2000 UTC (18 years, 8 months ago) by leunga
File length: 5216 byte(s)
Diff to previous 651

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

Revision 651 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jun 1 18:34:03 2000 UTC (19 years, 2 months ago) by monnier
File length: 5448 byte(s)
Diff to previous 585
bring revisions from the vendor branch to the trunk

Revision 585 - (view) (download) (annotate) - [select for diffs]
Modified Wed Mar 29 23:55:35 2000 UTC (19 years, 4 months ago) by leunga
File length: 5448 byte(s)
Diff to previous 579

   This update contains major changes to the code generator and various
back ends.  Please see the entry leunga-20000327-mlriscGen_hppa_alpha_x86
in the file sml/HISTORY for details.

Revision 579 - (view) (download) (annotate) - [select for diffs]
Modified Wed Mar 22 06:33:08 2000 UTC (19 years, 5 months ago) by leunga
File length: 5128 byte(s)
Diff to previous 555


1. X86 fixes/changes

   a.  x86Rewrite bug with MUL3 (found by Lal)
   b.  Added the instructions FSTS, FSTL

2. PA-RISC fixes/changes

   a.  B label should not be a delay slot candidate!  Why did this work?
   b.  ADDT(32, REG(32, r), LI n) now generates one instruction instead of two,
       as it should be.
   c.  The assembly syntax for fstds and fstdd was wrong.
   d.  Added the composite instruction COMICLR/LDO, which is the immediate
       operand variant of COMCLR/LDO.

3. Generic MLRISC

   a.  shuffle.sml rewritten to be slightly more efficient
   b.  DIV bug in mltree-simplify fixed (found by Fermin)

4. Register Allocator

   a.  I now release the interference graph earlier during spilling.
       May improve memory usage.

Revision 555 - (view) (download) (annotate) - [select for diffs]
Modified Fri Mar 3 16:10:30 2000 UTC (19 years, 5 months ago) by george
File length: 5120 byte(s)
Diff to previous 545
lal-20000303-new mltree -- take II

Revision 545 - (view) (download) (annotate) - [select for diffs]
Modified Thu Feb 24 13:56:44 2000 UTC (19 years, 6 months ago) by george
File length: 5088 byte(s)
Diff to previous 430
  Changes to MLTREE

Revision 430 - (view) (download) (annotate) - [select for diffs]
Modified Wed Sep 8 09:47:00 1999 UTC (19 years, 11 months ago) by monnier
File length: 5076 byte(s)
Copied from: sml/branches/SMLNJ/src/MLRISC/hppa/backpatch/hppaDelaySlotProps.sml revision 429
Diff to previous 429
This commit was generated by cvs2svn to compensate for changes in r429,
which included commits to RCS files with non-trunk default branches.

Revision 429 - (view) (download) (annotate) - [select for diffs]
Modified Wed Sep 8 09:47:00 1999 UTC (19 years, 11 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/hppa/backpatch/hppaDelaySlotProps.sml
File length: 5076 byte(s)
Diff to previous 410
version 110.21

Revision 410 - (view) (download) (annotate) - [select for diffs]
Modified Fri Sep 3 00:25:03 1999 UTC (19 years, 11 months ago) by
Original Path: sml/branches/SMLNJ/src/MLRISC/hppa/backpatch/hppaDelaySlotProps.sml
File length: 4923 byte(s)
Copied from: sml/trunk/src/MLRISC/hppa/backpatch/hppaDelaySlotProps.sml revision 409
Diff to previous 409
This commit was manufactured by cvs2svn to create branch 'SMLNJ'.

Revision 409 - (view) (download) (annotate) - [select for diffs]
Added Fri Sep 3 00:21:52 1999 UTC (19 years, 11 months ago) by monnier
File length: 4923 byte(s)
Initial revision

This form allows you to request diffs between any two revisions of this file. For each of the two "sides" of the diff, enter a numeric revision.

  Diffs between and
  Type of Diff should be a

Sort log by:

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0