Tested the jump chain elimination on all architectures (except the
hppa).  This is on by default right now and is profitable for the
alpha and x86, however, it may not be profitable for the sparc and ppc
when compiling the compiler.

The gc test will typically jump to a label at the end of the cluster,
where there is another jump to an external cluster containing the actual
code to invoke gc. This is to allow factoring of common gc invocation
sequences. That is to say, we generate:

	f:
	   testgc
	   ja	L1	% jump if above to L1

	L1:
	   jmp L2


After jump chain elimination the 'ja L1' instructions is converted to
'ja L2'. On the sparc and ppc, many of the 'ja L2' instructions may end
up being implemented in their long form (if L2 is far away) using:

	jbe	L3	% jump if below or equal to L3
        jmp 	L2
     L3:
	...


For large compilation units L2  may be far away.

  Changed representation of probabilities and frequencies.

Tested the weighted block placement optimization on all architectures
(except the hppa) using AMPL to generate the block and edge frequencies.
Changes were required in the machine properties to correctly
categorize trap instructions. There is an MLRISC flag
"weighted-block-placement" that can be used to enable weighted block
placement, but this will be ineffective without block/edge
frequencies (coming soon).

fixed downstream problems caused by those Freq type change in MLRISC

  Changed specification of negateConditional.

   There is a dramatic simplification in the interface to the
   register allocator for RISC architectures as a result of making
   parallel copy instructions explicit.

1. Since COPY instructions are no longer native to the architecture,
   a generic functor can be used to implement the expandCopies function.

2. Allowed EXPORT and IMPORT pseudo-op declarations to appear inside a
   TEXT segment.

	Removed the native COPY and FCOPY instructions
	from all the architectures and replaced it with the
	explicit COPY instruction from the previous commit.

	It is now possible to simplify many of the optimizations
	modules that manipulate copies. This has not been
	done in this change.

Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.

1. Made the stuff in MLRISC/Tools compile with the new pseudo ops changes.
2. Packaged the stuff in MLRISC/Tools as a library during installation.

  Implemented a complete redesign of MLRISC pseudo-ops. Now there
  ought to never be any question of incompatabilities with
  pseudo-op syntax expected by host assemblers.

  For now, only modules supporting GAS syntax are implemented
  but more should follow, such as MASM, and vendor assembler
  syntax, e.g. IBM as, Sun as, etc.

Substantial simplification in the CELLS interface

omit frame pointer optimization

   Support for alternative control-flow, exception handlers added.

    Merging the types labexp and mltree.
    tag leunga-20010111-labexp=mltree

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

     None of these changes should affect SML/NJ.  See HISTORY file for details.
     CVS Tag=leunga-20000609-various

bring revisions from the vendor branch to the trunk

   This update synchronizes my repository with Yale's.  Most of these
changes are related to C--, Moby, and my optimizations.  It should have
little impact on SML/NJ.

   CVS tag leunga-20000420-ssa-c---stuff

   This update contains major changes to the code generator and various
back ends.  Please see the entry leunga-20000327-mlriscGen_hppa_alpha_x86
in the file sml/HISTORY for details.

lal-20000303-new mltree -- take II

  Changes to MLTREE

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Initial revision

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Initial revision