fixed bug in RISC RA related to rewrite code for spills and reloads
of floating point registers;  nucleic now compiles again on the Sparc

   There is a dramatic simplification in the interface to the
   register allocator for RISC architectures as a result of making
   parallel copy instructions explicit.

	Removed the native COPY and FCOPY instructions
	from all the architectures and replaced it with the
	explicit COPY instruction from the previous commit.

	It is now possible to simplify many of the optimizations
	modules that manipulate copies. This has not been
	done in this change.

Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.

  Converted sml/nj files to use the new CellSet

Substantial simplification in the CELLS interface

   Support for alternative control-flow, exception handlers added.

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

     None of these changes should affect SML/NJ.  See HISTORY file for details.
     CVS Tag=leunga-20000609-various

bring revisions from the vendor branch to the trunk

   This update contains major changes to the code generator and various
back ends.  Please see the entry leunga-20000327-mlriscGen_hppa_alpha_x86
in the file sml/HISTORY for details.

lal-20000303-new mltree -- take II

  Changes to MLTREE

This commit was generated by cvs2svn to compensate for changes in r498,
which included commits to RCS files with non-trunk default branches.

This commit was generated by cvs2svn to compensate for changes in r469,
which included commits to RCS files with non-trunk default branches.

This commit was generated by cvs2svn to compensate for changes in r429,
which included commits to RCS files with non-trunk default branches.

This commit was generated by cvs2svn to compensate for changes in r411,
which included commits to RCS files with non-trunk default branches.

This commit was generated by cvs2svn to compensate for changes in r247,
which included commits to RCS files with non-trunk default branches.

This commit was generated by cvs2svn to compensate for changes in r245,
which included commits to RCS files with non-trunk default branches.

This commit was generated by cvs2svn to compensate for changes in r243,
which included commits to RCS files with non-trunk default branches.

Initial revision