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# SCM Repository

[smlnj] Diff of /sml/trunk/src/MLRISC/mltree/mltree-gen.sml
 [smlnj] / sml / trunk / src / MLRISC / mltree / mltree-gen.sml

# Diff of /sml/trunk/src/MLRISC/mltree/mltree-gen.sml

revision 1184, Fri Mar 29 22:22:22 2002 UTC revision 1185, Mon Apr 1 22:06:47 2002 UTC
# Line 91  Line 91
91      * The logic is as follows:      * The logic is as follows:
92      *    - if q > 0, then we are done since any rounding was      *    - if q > 0, then we are done since any rounding was
93      *      at the same time TO_ZERO and TO_NEGINF      *      at the same time TO_ZERO and TO_NEGINF
94        *      (This is the fast path that does not require calculating the remainder.)
95      *    - otherwise we calculate r and see if it is zero; if so, no adjustment      *    - otherwise we calculate r and see if it is zero; if so, no adjustment
96      *    - finally if r and b have the same sign (i.e., r XOR b >= 0)      *    - finally if r and b have the same sign (i.e., r XOR b >= 0)
97      *      we still don't need adjustment      *      we still don't need adjustment
99        *
100        * Instruction selection for machines (e.g., x86) where the hardware returns both
101        * q and r anyway should implement this logic directly.
102        *)
103     fun divinf (xdiv, ty, aexp, bexp) = let     fun divinf (xdiv, ty, aexp, bexp) = let
104         val a = Cells.newReg ()         val a = Cells.newReg ()
105         val b = Cells.newReg ()         val b = Cells.newReg ()
# Line 126  Line 131
131     end     end
132
133     (* Same for rem when rounding to negative infinity.     (* Same for rem when rounding to negative infinity.
134        * Since we have to return (and therefore calculate) the remainder anyway,
135        * we can skip the q > 0 test because it will be caught by the samesign(r,b)
136        * test.
137        *
138      * The odd case is when a = MININT and b = -1 in which case the DIVS op      * The odd case is when a = MININT and b = -1 in which case the DIVS op
139      * will overflow and trap on some machines.  On others the result      * will overflow and trap on some machines.  On others the result
140      * will be bogus.  Should we fix that? *)      * will be bogus.  Should we fix that? *)
# Line 145  Line 154
154            T.MV (ty, r, T.SUB (ty, T.REG (ty, a),            T.MV (ty, r, T.SUB (ty, T.REG (ty, a),
155                                    T.MULS (ty, T.REG (ty, q),                                    T.MULS (ty, T.REG (ty, q),
156                                                T.REG (ty, b)))),                                                T.REG (ty, b)))),
T.IF (T.CMP (ty, T.Basis.GT, T.REG (ty, q), zero),
T.SEQ [],
157                  T.IF (T.CMP (ty, T.Basis.EQ, T.REG (ty, r), zero),                  T.IF (T.CMP (ty, T.Basis.EQ, T.REG (ty, r), zero),
158                        T.SEQ [],                        T.SEQ [],
159                        T.IF (T.CMP (ty, T.Basis.GE,                        T.IF (T.CMP (ty, T.Basis.GE,
160                                     T.XORB (ty, T.REG (ty, b), T.REG (ty, r)),                                     T.XORB (ty, T.REG (ty, b), T.REG (ty, r)),
161                                     zero),                                     zero),
162                              T.SEQ [],                              T.SEQ [],
163                              T.MV (ty, r, T.ADD (ty, T.REG (ty, r),                        T.MV (ty, r, T.ADD (ty, T.REG (ty, r), T.REG (ty, b)))))],
T.REG (ty, b))))))],
164                T.REG (ty, r))                T.REG (ty, r))
165     end     end
166
167     (* Same for rem when rounding when rounding to zero. *)     (* Same for rem when rounding to zero. *)
168     fun remzero (xdiv, xmul, ty, aexp, bexp) = let     fun remzero (xdiv, xmul, ty, aexp, bexp) = let
169         val a = Cells.newReg ()         val a = Cells.newReg ()
170         val b = Cells.newReg ()         val b = Cells.newReg ()

Legend:
 Removed from v.1184 changed lines Added in v.1185