Added IBM syntax support for PowerPC.

   More PPC instructions added.

   Added LWARX and STWCX to the Power PC instruction set.

     Changed mdl gen to make it compile.
     x86 asssembly fix for fcmpi.

implemented generic Controls module and used it for
all compiler flags/tuneable knobs/...;
more command-line options accepted (for setting the above controls);
some minor bug fixes

In order to support the block placement optimization, the first
cluster that is generated (called the linkage cluster) contains a jump
to the entry point for the compilation unit. The linkage cluster
contains only one 'function', so block placement will have no effect on
the linkage cluster itself, but all the other clusters have full
freedom in the manner in which they reorder blocks or functions.

On the x86 the typical linkage code that is generated is:
   ----------------------
	.align 2
   L0:
        addl    $L1-L0, 72(%esp)
        jmp     L0


        .align  2
   L1:
   ----------------------

72(%esp) is the memory location for the stdlink register. This
must contain the address of the CPS function being called. In the
above example, it contains the address of  L0; before
calling L1 (the real entry point for the compilation unit), it
must contain the address for L1, and hence

	addl $L1-L0, 72(%esp)

I have tested this on all architectures except the hppa.The increase
in code size is of course negligible.

  removed extra blank line when printing annotations in assembly code

  fixed various bugs with emitting pseudo-ops

	Removed the native COPY and FCOPY instructions
	from all the architectures and replaced it with the
	explicit COPY instruction from the previous commit.

	It is now possible to simplify many of the optimizations
	modules that manipulate copies. This has not been
	done in this change.

Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.

  Implemented a complete redesign of MLRISC pseudo-ops. Now there
  ought to never be any question of incompatabilities with
  pseudo-op syntax expected by host assemblers.

  For now, only modules supporting GAS syntax are implemented
  but more should follow, such as MASM, and vendor assembler
  syntax, e.g. IBM as, Sun as, etc.

Updated input to PERL scripts used to generate
MLRISC cm files.

removed clusters from MLRISC

  Moved CellSets from Cells to CellsBasis.

Substantial simplification in the CELLS interface

omit frame pointer optimization

    Moby related MLRISC changes

Port to Mac OS X

   Support for alternative control-flow, exception handlers added.

    Merging the types labexp and mltree.
    tag leunga-20010111-labexp=mltree

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

     None of these changes should affect SML/NJ.  See HISTORY file for details.
     CVS Tag=leunga-20000609-various

bring revisions from the vendor branch to the trunk

   This update synchronizes my repository with Yale's.  Most of these
changes are related to C--, Moby, and my optimizations.  It should have
little impact on SML/NJ.

   CVS tag leunga-20000420-ssa-c---stuff

      Changes to assembly output and fixes a bug in the x86 assembler
      CVS tag=leunga-20000404-x86-asm

  Changes to MLTREE

This commit was generated by cvs2svn to compensate for changes in r498,
which included commits to RCS files with non-trunk default branches.

version 110.25

version 110.23

version 110.21

version 110.19

version 110.16