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[smlnj] Log of /sml/trunk/src/MLRISC/ppc/instructions/ppcShuffle.sml
[smlnj] / sml / trunk / src / MLRISC / ppc / instructions / ppcShuffle.sml  
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Log of /sml/trunk/src/MLRISC/ppc/instructions/ppcShuffle.sml

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(Current path doesn't exist after revision 2125)

Revision 1033 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jan 24 05:45:18 2002 UTC (17 years, 8 months ago) by george
File length: 1236 byte(s)
Diff to previous 1003
   There is a dramatic simplification in the interface to the
   register allocator for RISC architectures as a result of making
   parallel copy instructions explicit.

Revision 1003 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 7 02:45:32 2001 UTC (17 years, 10 months ago) by george
File length: 1203 byte(s)
Diff to previous 889
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.

Revision 889 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jul 19 20:35:20 2001 UTC (18 years, 3 months ago) by george
File length: 1203 byte(s)
Diff to previous 744
Substantial simplification in the CELLS interface

Revision 744 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 8 04:11:42 2000 UTC (18 years, 10 months ago) by leunga
File length: 1189 byte(s)
Diff to previous 651

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

Revision 651 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jun 1 18:34:03 2000 UTC (19 years, 4 months ago) by monnier
File length: 1228 byte(s)
Diff to previous 430
bring revisions from the vendor branch to the trunk

Revision 430 - (view) (download) (annotate) - [select for diffs]
Modified Wed Sep 8 09:47:00 1999 UTC (20 years, 1 month ago) by monnier
File length: 1228 byte(s)
Copied from: sml/branches/SMLNJ/src/MLRISC/ppc/instructions/ppcShuffle.sml revision 429
Diff to previous 429
This commit was generated by cvs2svn to compensate for changes in r429,
which included commits to RCS files with non-trunk default branches.

Revision 429 - (view) (download) (annotate) - [select for diffs]
Modified Wed Sep 8 09:47:00 1999 UTC (20 years, 1 month ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/ppc/instructions/ppcShuffle.sml
File length: 1228 byte(s)
Diff to previous 411
version 110.21

Revision 411 - (view) (download) (annotate) - [select for diffs]
Modified Fri Sep 3 00:25:03 1999 UTC (20 years, 1 month ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/ppc/instructions/ppcShuffle.sml
File length: 1260 byte(s)
Diff to previous 245
version 110.19

Revision 245 - (view) (download) (annotate) - [select for diffs]
Added Sat Apr 17 18:47:12 1999 UTC (20 years, 6 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/ppc/instructions/ppcShuffle.sml
File length: 1123 byte(s)
version 110.16

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