Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] View of /sml/trunk/src/MLRISC/ra/arch-spill-instr.sig
ViewVC logotype

View of /sml/trunk/src/MLRISC/ra/arch-spill-instr.sig

Parent Directory Parent Directory | Revision Log Revision Log


Revision 1033 - (download) (as text) (annotate)
Thu Jan 24 05:45:18 2002 UTC (17 years, 6 months ago) by george
File size: 1024 byte(s)
   There is a dramatic simplification in the interface to the
   register allocator for RISC architectures as a result of making
   parallel copy instructions explicit.
(* arch-spill-instr.sig
 *
 * COPYRIGHT (c) 2002 Bell Labs, Lucent Technologies
 *
 * Architecture specific instructions to emit when spilling an instruction.
 *)

(* TODO: Some day, all these interface functions will be sensitive to
 * the size being spilled or reloaded --- but today is not the day!
 *)
signature ARCH_SPILL_INSTR = sig
  structure I : INSTRUCTIONS
  structure CB : CELLS_BASIS = CellsBasis
  
  val spillToEA :
      CB.cellkind ->
         CB.cell * I.ea -> 
            {code:I.instruction list, proh:CB.cell list, newReg:CB.cell option}

  val reloadFromEA :
      CB.cellkind ->
         CB.cell * I.ea ->
            {code:I.instruction list, proh:CB.cell list, newReg:CB.cell option}	   

  val spill : 
      CB.cellkind -> 
         I.instruction * CB.cell * I.ea -> 
	    {code:I.instruction list, proh:CB.cell list, newReg:CB.cell option}
  val reload : 
      CB.cellkind ->
         I.instruction * CB.cell * I.ea -> 
		 {code:I.instruction list, proh:CB.cell list, newReg:CB.cell option}
end

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0