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View of /sml/trunk/src/MLRISC/ra/ra-core.sig

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Revision 579 - (download) (as text) (annotate)
Wed Mar 22 06:33:08 2000 UTC (19 years, 7 months ago) by leunga
File size: 4130 byte(s)


1. X86 fixes/changes

   a.  x86Rewrite bug with MUL3 (found by Lal)
   b.  Added the instructions FSTS, FSTL

2. PA-RISC fixes/changes

   a.  B label should not be a delay slot candidate!  Why did this work?
   b.  ADDT(32, REG(32, r), LI n) now generates one instruction instead of two,
       as it should be.
   c.  The assembly syntax for fstds and fstdd was wrong.
   d.  Added the composite instruction COMICLR/LDO, which is the immediate
       operand variant of COMCLR/LDO.

3. Generic MLRISC

   a.  shuffle.sml rewritten to be slightly more efficient
   b.  DIV bug in mltree-simplify fixed (found by Fermin)

4. Register Allocator

   a.  I now release the interference graph earlier during spilling.
       May improve memory usage.
(*
 * Note: This is the core of the new register allocator, i.e. the portion
 * that manipulates only the interference graph and not the flowgraph.
 *
 * -- Allen
 *)

signature RA_CORE = 
sig

   structure G  : RA_GRAPH
   structure BM :
   sig 
      val member : G.bitMatrix -> int * int -> bool
      val add    : G.bitMatrix -> int * int -> bool
   end
   structure MV : RA_PRIORITY_QUEUE where type elem = G.move
   structure FZ : RA_PRIORITY_QUEUE where type elem = G.node

   type move_queue
   type freeze_queue

   val NO_OPTIMIZATION      : G.mode
   val BIASED_SELECTION     : G.mode
   val DEAD_COPY_ELIM       : G.mode
   val COMPUTE_SPAN         : G.mode
   val SAVE_COPY_TEMPS      : G.mode
   val HAS_PARALLEL_COPIES  : G.mode

   (*
    * Basic functions
    *)

   (* dump the interference graph to a stream *)
   val dumpGraph : G.interferenceGraph -> TextIO.outstream -> unit
   val show      : G.interferenceGraph -> G.node -> string

   (* add an edge to the interference graph *)
   val addEdge : G.interferenceGraph -> G.node * G.node -> unit

   (* remove an edge from the interference graph *)
   val removeEdge : G.interferenceGraph -> G.node * G.node -> unit

   (*
    * Function to create new nodes 
    *)
   val newNodes : G.interferenceGraph -> 
        {cost:int,pt:G.programPoint,defs:int list,uses:int list} -> 
            G.node list (* defs *)

   (*
    * Update regmap after finishing register allocation or copy propagation
    *)
   val finishRA : G.interferenceGraph -> unit
   val finishCP : G.interferenceGraph -> unit

   (*
    * Create an initial set of worklists from a new interference graph
    * and a list of moves 
    *)
   val initWorkLists : G.interferenceGraph -> 
          { moves : G.move list
          } -> 
          { simplifyWkl : G.node list, 
            moveWkl     : move_queue, 
            freezeWkl   : freeze_queue, 
            spillWkl    : G.node list   (* high degreee nodes *)
          }

   (*
    * Clear the interference graph but keep the nodes table intact 
    *)
   val clearGraph : G.interferenceGraph -> unit

   (*
    * Remove all adjacency lists from the nodes table.
    *)
   val clearNodes : G.interferenceGraph -> unit

   (*
    * Return a regmap function that reflects the current interference graph.
    * Spilled registers are given the special value ~1
    *)
   val regmap      : G.interferenceGraph -> (int -> int)
   val spillRegmap : G.interferenceGraph -> (int -> int)
   val spillLoc    : G.interferenceGraph -> (int -> int)

   (* 
    * Simplify, Coalease and Freeze until the work list is done
    *)
   val iteratedCoalescing : 
        G.interferenceGraph -> 
           { simplifyWkl : G.node list, 
             moveWkl     : move_queue,
             freezeWkl   : freeze_queue,
             stack       : G.node list
           } ->
           { stack : G.node list 
           }

   (* 
    * potentially spill a node.
    *)
   val potentialSpillNode : 
        G.interferenceGraph ->
           { node  : G.node,
             cost  : real,
             stack : G.node list
           } ->
           { moveWkl   : move_queue,
             freezeWkl : freeze_queue,
             stack     : G.node list
           }

   (*
    * Color nodes on the stack, using Briggs' optimistic spilling.  
    * Return a list of actual spills 
    *)
   val select : 
        G.interferenceGraph -> 
           { stack  : G.node list 
           } ->
           { spills : G.node list (* actual spills *)
           }

   (*
    * Incorporate memory <-> register moves
    *)
   val initMemMoves : G.interferenceGraph -> unit

   (*
    * Compute spill savings due to memory <-> register moves
    *)
   val moveSavings : G.interferenceGraph -> (int -> int)

   (*
    * Spill propagation/coalescing phase 
    *)
   (*
   val spillPropagation : G.interferenceGraph -> G.node list -> G.node list

   (*
    * Spill coalescing phase
    *)
   val spillCoalescing : G.interferenceGraph -> G.node list -> unit

   (*
    * Spill coloring phase
    *)
   val spillColoring : G.interferenceGraph -> G.node list -> unit
   *)

end

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