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[smlnj] Log of /sml/trunk/src/MLRISC/ra/risc-ra.sml
[smlnj] / sml / trunk / src / MLRISC / ra / risc-ra.sml  
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Log of /sml/trunk/src/MLRISC/ra/risc-ra.sml

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Revision 1126 - (view) (download) (annotate) - [select for diffs]
Modified Thu Mar 7 21:16:28 2002 UTC (17 years, 3 months ago) by blume
File length: 12736 byte(s)
Diff to previous 1033
implemented generic Controls module and used it for
all compiler flags/tuneable knobs/...;
more command-line options accepted (for setting the above controls);
some minor bug fixes

Revision 1033 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jan 24 05:45:18 2002 UTC (17 years, 5 months ago) by george
File length: 12782 byte(s)
Diff to previous 1009
   There is a dramatic simplification in the interface to the
   register allocator for RISC architectures as a result of making
   parallel copy instructions explicit.

Revision 1009 - (view) (download) (annotate) - [select for diffs]
Modified Wed Jan 9 19:44:22 2002 UTC (17 years, 5 months ago) by george
File length: 13417 byte(s)
Diff to previous 1003
	Removed the native COPY and FCOPY instructions
	from all the architectures and replaced it with the
	explicit COPY instruction from the previous commit.

	It is now possible to simplify many of the optimizations
	modules that manipulate copies. This has not been
	done in this change.

Revision 1003 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 7 02:45:32 2001 UTC (17 years, 6 months ago) by george
File length: 13446 byte(s)
Diff to previous 984
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

	type instruction

	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	f1 := f2 + f3

but now generate:

	f1 := f2 + f3
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction

where lda is just (INSTR o LDA), etc.

Revision 984 - (view) (download) (annotate) - [select for diffs]
Modified Wed Nov 21 19:00:08 2001 UTC (17 years, 7 months ago) by george
File length: 11373 byte(s)
Diff to previous 933
  Implemented a complete redesign of MLRISC pseudo-ops. Now there
  ought to never be any question of incompatabilities with
  pseudo-op syntax expected by host assemblers.

  For now, only modules supporting GAS syntax are implemented
  but more should follow, such as MASM, and vendor assembler
  syntax, e.g. IBM as, Sun as, etc.

Revision 933 - (view) (download) (annotate) - [select for diffs]
Modified Wed Sep 19 19:31:19 2001 UTC (17 years, 9 months ago) by george
File length: 11370 byte(s)
Diff to previous 909

Revision 909 - (view) (download) (annotate) - [select for diffs]
Modified Fri Aug 24 17:48:53 2001 UTC (17 years, 10 months ago) by george
File length: 11365 byte(s)
Diff to previous 889
removed clusters from MLRISC

Revision 889 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jul 19 20:35:20 2001 UTC (17 years, 11 months ago) by george
File length: 11376 byte(s)
Diff to previous 823
Substantial simplification in the CELLS interface

Revision 823 - (view) (download) (annotate) - [select for diffs]
Modified Tue May 8 21:25:15 2001 UTC (18 years, 1 month ago) by george
File length: 11219 byte(s)
Diff to previous 815
omit frame pointer optimization

Revision 815 - (view) (download) (annotate) - [select for diffs]
Modified Fri May 4 05:09:10 2001 UTC (18 years, 1 month ago) by leunga
File length: 10832 byte(s)
Diff to previous 796

    Moby related MLRISC changes

Revision 796 - (view) (download) (annotate) - [select for diffs]
Modified Tue Mar 6 00:04:33 2001 UTC (18 years, 3 months ago) by leunga
File length: 10824 byte(s)
Diff to previous 744

   Support for alternative control-flow, exception handlers added.

Revision 744 - (view) (download) (annotate) - [select for diffs]
Added Fri Dec 8 04:11:42 2000 UTC (18 years, 6 months ago) by leunga
File length: 10497 byte(s)

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

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