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[smlnj] Annotation of /sml/trunk/src/MLRISC/scheduling/dagScheduling.sml
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Annotation of /sml/trunk/src/MLRISC/scheduling/dagScheduling.sml

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Revision 695 - (view) (download)

1 : leunga 695 (*
2 :     * A region based scheduler.
3 :     *
4 :     * -- Allen
5 :     *)
6 :    
7 :     functor DAGScheduling
8 :     (structure ListScheduler : LIST_SCHEDULER
9 :     structure DDGBuilder : SCHEDULER_DDG_BUILDER
10 :     structure Ranks : SCHEDULING_RANKS
11 :     where type edge = DDGBuilder.DDG.edge
12 :     structure Viewer : GLOBAL_SCHEDULER_DDG_VIEWER
13 :     sharing DDGBuilder.DDG = ListScheduler.DDG = Ranks.DDG
14 :     sharing DDGBuilder.CFG = ListScheduler.CFG
15 :     sharing Viewer.IR = ListScheduler.IR
16 :     sharing Viewer.DDG = DDGBuilder.DDG
17 :     ) : GLOBAL_SCHEDULING_ALGORITHM =
18 :     struct
19 :     structure IR = ListScheduler.IR
20 :     structure CFG = ListScheduler.CFG
21 :     structure DDG = ListScheduler.DDG
22 :     structure G = Graph
23 :    
24 :     val i2s = Int.toString
25 :    
26 :     val view_IR = MLRiscControl.getFlag "view-IR"
27 :    
28 :     fun schedule cpu_info { ir, region, numberOfInstructions, blockIdTbl } =
29 :     let val DDG as G.GRAPH ddg =
30 :     DDGBuilder.buildDDG {cpu_info=cpu_info,
31 :     cfg=region, blockIdTbl=blockIdTbl,
32 :     numberOfInstructions=numberOfInstructions}
33 :     val _ = print("V(ddg)="^i2s(#order ddg ())^
34 :     " E(ddg)="^i2s(#size ddg ())^"\n")
35 :     val _ = if !view_IR then Viewer.view ir DDG else ()
36 :     val ranking = Ranks.rank DDG
37 :     in ListScheduler.listScheduler
38 :     {cpu_info=cpu_info,
39 :     blockIdTbl=blockIdTbl,
40 :     cfg=ir,
41 :     region=region,
42 :     ddg=DDG,
43 :     ranking=ranking
44 :     }
45 :     end
46 :    
47 :     end

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