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[smlnj] View of /sml/trunk/src/MLRISC/sparc/instructions/sparccomp-instr-ext.sml
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View of /sml/trunk/src/MLRISC/sparc/instructions/sparccomp-instr-ext.sml

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Revision 1003 - (download) (annotate)
Fri Dec 7 02:45:32 2001 UTC (18 years, 1 month ago) by george
File size: 1338 byte(s)
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

	type instruction

	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	f1 := f2 + f3

but now generate:

	f1 := f2 + f3
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction

where lda is just (INSTR o LDA), etc.
(* sparccomp-instr-ext.sml
 * COPYRIGHT (c) 2001 Bell Labs, Lucent Technologies
 * compiling a trivial extensions to the Sparc instruction set
 * (UNIMP instruction)
signature SPARCCOMP_INSTR_EXT = sig
    structure T : MLTREE
    structure I : SPARCINSTR
    		where T = T
    structure TS : MLTREE_STREAM
		where T = I.T
    structure CFG : CONTROL_FLOW_GRAPH 
    		where I = I 

    type reducer =
	 (I.instruction, I.C.cellset, I.operand, I.addressing_mode, CFG.cfg) TS.reducer

    val compileSext :
	-> { stm: (T.stm, T.rexp, T.fexp, T.ccexp) SparcInstrExt.sext,
	     an: T.an list }
	-> unit

functor SparcCompInstrExt 
  (structure I   : SPARCINSTR
   structure TS  : MLTREE_STREAM
		where T = I.T
   structure CFG : CONTROL_FLOW_GRAPH 
   		where I = I
                  and P = TS.S.P
    structure CFG = CFG
    structure T = TS.T
    structure TS = TS
    structure I = I
    structure C = I.C
    structure X = SparcInstrExt

    type stm = (T.stm, T.rexp, T.fexp, T.ccexp) X.sext

    type reducer =
	 (I.instruction, I.C.cellset, I.operand, I.addressing_mode, CFG.cfg) TS.reducer

    fun compileSext reducer { stm: stm, an: T.an list } = let
	val TS.REDUCER { emit, ... } = reducer
	case stm of X.UNIMP i => emit (I.unimp {const22 = i}, an)

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