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[smlnj] View of /sml/trunk/src/MLRISC/sparc/instructions/sparccomp-instr-ext.sml
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View of /sml/trunk/src/MLRISC/sparc/instructions/sparccomp-instr-ext.sml

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Revision 984 - (download) (annotate)
Wed Nov 21 19:00:08 2001 UTC (18 years, 7 months ago) by george
File size: 1338 byte(s)
  Implemented a complete redesign of MLRISC pseudo-ops. Now there
  ought to never be any question of incompatabilities with
  pseudo-op syntax expected by host assemblers.

  For now, only modules supporting GAS syntax are implemented
  but more should follow, such as MASM, and vendor assembler
  syntax, e.g. IBM as, Sun as, etc.
(* sparccomp-instr-ext.sml
 *
 * COPYRIGHT (c) 2001 Bell Labs, Lucent Technologies
 *
 * compiling a trivial extensions to the Sparc instruction set
 * (UNIMP instruction)
 *)
signature SPARCCOMP_INSTR_EXT = sig
    structure T : MLTREE
    structure I : SPARCINSTR
    		where T = T
    structure TS : MLTREE_STREAM
		where T = I.T
    structure CFG : CONTROL_FLOW_GRAPH 
    		where I = I 


    type reducer =
	 (I.instruction, I.C.cellset, I.operand, I.addressing_mode, CFG.cfg) TS.reducer

    val compileSext :
	reducer
	-> { stm: (T.stm, T.rexp, T.fexp, T.ccexp) SparcInstrExt.sext,
	     an: T.an list }
	-> unit
end

functor SparcCompInstrExt 
  (structure I   : SPARCINSTR
   structure TS  : MLTREE_STREAM
		where T = I.T
   structure CFG : CONTROL_FLOW_GRAPH 
   		where I = I
                  and P = TS.S.P
  ) : SPARCCOMP_INSTR_EXT = 
struct
    structure CFG = CFG
    structure T = TS.T
    structure TS = TS
    structure I = I
    structure C = I.C
    structure X = SparcInstrExt

    type stm = (T.stm, T.rexp, T.fexp, T.ccexp) X.sext

    type reducer =
	 (I.instruction, I.C.cellset, I.operand, I.addressing_mode, CFG.cfg) TS.reducer

    fun compileSext reducer { stm: stm, an: T.an list } = let
	val TS.REDUCER { emit, ... } = reducer
    in
	case stm of X.UNIMP i => emit (I.UNIMP {const22 = i}, an)
    end
end

root@smlnj-gforge.cs.uchicago.edu
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