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[smlnj] Log of /sml/trunk/src/MLRISC/x86/backpatch
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Log of /sml/trunk/src/MLRISC/x86/backpatch

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Revision 1009 - Directory Listing
Modified Wed Jan 9 19:44:22 2002 UTC (17 years, 6 months ago) by george
	Removed the native COPY and FCOPY instructions
	from all the architectures and replaced it with the
	explicit COPY instruction from the previous commit.

	It is now possible to simplify many of the optimizations
	modules that manipulate copies. This has not been
	done in this change.

Revision 1003 - Directory Listing
Modified Fri Dec 7 02:45:32 2001 UTC (17 years, 7 months ago) by george
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

	type instruction

	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	f1 := f2 + f3

but now generate:

	f1 := f2 + f3
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction

where lda is just (INSTR o LDA), etc.

Revision 984 - Directory Listing
Modified Wed Nov 21 19:00:08 2001 UTC (17 years, 8 months ago) by george
  Implemented a complete redesign of MLRISC pseudo-ops. Now there
  ought to never be any question of incompatabilities with
  pseudo-op syntax expected by host assemblers.

  For now, only modules supporting GAS syntax are implemented
  but more should follow, such as MASM, and vendor assembler
  syntax, e.g. IBM as, Sun as, etc.

Revision 744 - Directory Listing
Modified Fri Dec 8 04:11:42 2000 UTC (18 years, 7 months ago) by leunga

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

Revision 651 - Directory Listing
Modified Thu Jun 1 18:34:03 2000 UTC (19 years, 1 month ago) by monnier
bring revisions from the vendor branch to the trunk

Revision 579 - Directory Listing
Modified Wed Mar 22 06:33:08 2000 UTC (19 years, 4 months ago) by leunga

1. X86 fixes/changes

   a.  x86Rewrite bug with MUL3 (found by Lal)
   b.  Added the instructions FSTS, FSTL

2. PA-RISC fixes/changes

   a.  B label should not be a delay slot candidate!  Why did this work?
   b.  ADDT(32, REG(32, r), LI n) now generates one instruction instead of two,
       as it should be.
   c.  The assembly syntax for fstds and fstdd was wrong.
   d.  Added the composite instruction COMICLR/LDO, which is the immediate
       operand variant of COMCLR/LDO.

3. Generic MLRISC

   a.  shuffle.sml rewritten to be slightly more efficient
   b.  DIV bug in mltree-simplify fixed (found by Fermin)

4. Register Allocator

   a.  I now release the interference graph earlier during spilling.
       May improve memory usage.

Revision 565 - Directory Listing
Modified Sun Mar 5 04:10:18 2000 UTC (19 years, 4 months ago) by leunga

Fix up a few floating point bugs on the x86 that are discovered by Fermin.
Rewritten the Sethi-Ullman code.  Added new FP instructions to the x86,
including FIxxxx, FCOMxx, and FLDxx.

Revision 555 - Directory Listing
Modified Fri Mar 3 16:10:30 2000 UTC (19 years, 4 months ago) by george
lal-20000303-new mltree -- take II

Revision 545 - Directory Listing
Modified Thu Feb 24 13:56:44 2000 UTC (19 years, 5 months ago) by george
  Changes to MLTREE

Revision 412 - Directory Listing
Modified Fri Sep 3 00:25:03 1999 UTC (19 years, 10 months ago) by monnier
This commit was generated by cvs2svn to compensate for changes in r411,
which included commits to RCS files with non-trunk default branches.

Revision 248 - Directory Listing
Modified Sat Apr 17 18:47:13 1999 UTC (20 years, 3 months ago) by monnier
This commit was generated by cvs2svn to compensate for changes in r247,
which included commits to RCS files with non-trunk default branches.

Revision 246 - Directory Listing
Modified Sat Apr 17 18:47:12 1999 UTC (20 years, 3 months ago) by monnier
This commit was generated by cvs2svn to compensate for changes in r245,
which included commits to RCS files with non-trunk default branches.

Revision 241 - Directory Listing
Added Sat Apr 17 18:35:00 1999 UTC (20 years, 3 months ago) by monnier
Initial revision

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