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[smlnj] Diff of /sml/trunk/src/MLRISC/x86/emit/x86Asm.sml
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Diff of /sml/trunk/src/MLRISC/x86/emit/x86Asm.sml

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revision 554, Thu Mar 2 21:29:44 2000 UTC revision 555, Fri Mar 3 16:10:30 2000 UTC
# Line 9  Line 9 
9                        structure Shuffle : X86SHUFFLE                        structure Shuffle : X86SHUFFLE
10                           where I = Instr                           where I = Instr
11    
12  (*#line 164.7 "x86/x86.md"*)  (*#line 171.7 "x86/x86.md"*)
13                        structure MemRegs : MEMORY_REGISTERS where I=Instr                        structure MemRegs : MEMORY_REGISTERS where I=Instr
14                       ) : INSTRUCTION_EMITTER =                       ) : INSTRUCTION_EMITTER =
15  struct  struct
# Line 145  Line 145 
145       | asm_move (I.MOVZBL) = "movzbl"       | asm_move (I.MOVZBL) = "movzbl"
146     and emit_move x = emit (asm_move x)     and emit_move x = emit (asm_move x)
147     and asm_fbinOp (I.FADDP) = "faddp"     and asm_fbinOp (I.FADDP) = "faddp"
148       | asm_fbinOp (I.FADD) = "fadd"       | asm_fbinOp (I.FADDS) = "fadds"
149       | asm_fbinOp (I.FIADD) = "fiadd"       | asm_fbinOp (I.FIADDS) = "fiadds"
150       | asm_fbinOp (I.FMULP) = "fmulp"       | asm_fbinOp (I.FMULP) = "fmulp"
151       | asm_fbinOp (I.FMUL) = "fmul"       | asm_fbinOp (I.FMULS) = "fmuls"
152       | asm_fbinOp (I.FIMUL) = "fimul"       | asm_fbinOp (I.FIMULS) = "fimuls"
153       | asm_fbinOp (I.FSUBP) = "fsubp"       | asm_fbinOp (I.FSUBP) = "fsubp"
154       | asm_fbinOp (I.FSUB) = "fsub"       | asm_fbinOp (I.FSUBS) = "fsubs"
155       | asm_fbinOp (I.FISUB) = "fisub"       | asm_fbinOp (I.FISUBS) = "fisubs"
156       | asm_fbinOp (I.FSUBRP) = "fsubrp"       | asm_fbinOp (I.FSUBRP) = "fsubrp"
157       | asm_fbinOp (I.FSUBR) = "fsubr"       | asm_fbinOp (I.FSUBRS) = "fsubrs"
158       | asm_fbinOp (I.FISUBR) = "fisubr"       | asm_fbinOp (I.FISUBRS) = "fisubrs"
159       | asm_fbinOp (I.FDIVP) = "fdivp"       | asm_fbinOp (I.FDIVP) = "fdivp"
160       | asm_fbinOp (I.FDIV) = "fdiv"       | asm_fbinOp (I.FDIVS) = "fdivs"
161       | asm_fbinOp (I.FIDIV) = "fidiv"       | asm_fbinOp (I.FIDIVS) = "fidivs"
162       | asm_fbinOp (I.FDIVRP) = "fdivrp"       | asm_fbinOp (I.FDIVRP) = "fdivrp"
163       | asm_fbinOp (I.FDIVR) = "fdivr"       | asm_fbinOp (I.FDIVRS) = "fdivrs"
164       | asm_fbinOp (I.FIDIVR) = "fidivr"       | asm_fbinOp (I.FIDIVRS) = "fidivrs"
165         | asm_fbinOp (I.FADDL) = "faddl"
166         | asm_fbinOp (I.FIADDL) = "fiaddl"
167         | asm_fbinOp (I.FMULL) = "fmull"
168         | asm_fbinOp (I.FIMULL) = "fimull"
169         | asm_fbinOp (I.FSUBL) = "fsubl"
170         | asm_fbinOp (I.FISUBL) = "fisubl"
171         | asm_fbinOp (I.FSUBRL) = "fsubrl"
172         | asm_fbinOp (I.FISUBRL) = "fisubrl"
173         | asm_fbinOp (I.FDIVL) = "fdivl"
174         | asm_fbinOp (I.FIDIVL) = "fidivl"
175         | asm_fbinOp (I.FDIVRL) = "fdivrl"
176         | asm_fbinOp (I.FIDIVRL) = "fidivrl"
177     and emit_fbinOp x = emit (asm_fbinOp x)     and emit_fbinOp x = emit (asm_fbinOp x)
178     and asm_funOp (I.FABS) = "fabs"     and asm_funOp (I.FABS) = "fabs"
179       | asm_funOp (I.FCHS) = "fchs"       | asm_funOp (I.FCHS) = "fchs"
# Line 182  Line 194 
194       | asm_fenvOp (I.FNSTENV) = "fnstenv"       | asm_fenvOp (I.FNSTENV) = "fnstenv"
195     and emit_fenvOp x = emit (asm_fenvOp x)     and emit_fenvOp x = emit (asm_fenvOp x)
196    
197  (*#line 166.6 "x86/x86.md"*)  (*#line 173.6 "x86/x86.md"*)
198     val memReg = MemRegs.memReg regmap     val memReg = MemRegs.memReg regmap
199    
200  (*#line 167.6 "x86/x86.md"*)  (*#line 174.6 "x86/x86.md"*)
201     fun emitInt32 i = let     fun emitInt32 i = let
202    
203  (*#line 168.10 "x86/x86.md"*)  (*#line 175.10 "x86/x86.md"*)
204            val s = Int32.toString i            val s = Int32.toString i
205    
206  (*#line 169.10 "x86/x86.md"*)  (*#line 176.10 "x86/x86.md"*)
207            val s = (if (i >= 0)            val s = (if (i >= 0)
208                   then s                   then s
209                   else ("-" ^ (String.substring (s, 1, (size s) - 1))))                   else ("-" ^ (String.substring (s, 1, (size s) - 1))))
# Line 199  Line 211 
211         end         end
212    
213    
214  (*#line 172.6 "x86/x86.md"*)  (*#line 179.6 "x86/x86.md"*)
215     fun emitScale 0 = emit "1"     fun emitScale 0 = emit "1"
216       | emitScale 1 = emit "2"       | emitScale 1 = emit "2"
217       | emitScale 2 = emit "4"       | emitScale 2 = emit "4"
# Line 221  Line 233 
233        | I.Relative _ => error "emit_operand"        | I.Relative _ => error "emit_operand"
234        | I.Direct r => emit_GP r        | I.Direct r => emit_GP r
235        | I.MemReg r => emit_operand (memReg opn)        | I.MemReg r => emit_operand (memReg opn)
236        | I.FDirect f => let        | I.ST f => emit_FP f
237          | I.FDirect f => emit_operand (memReg opn)
 (*#line 191.17 "x86/x86.md"*)  
            val f' = regmap f  
         in (if (f' < (32 + 8))  
               then (emit_FP f')  
               else (emit_operand (memReg opn)))  
         end  
   
238        | I.Displace{base, disp, mem, ...} =>        | I.Displace{base, disp, mem, ...} =>
239          ( emit_disp disp;          ( emit_disp disp;
240          emit "(";          emit "(";
# Line 260  Line 265 
265       | emit_disp (I.ImmedLabel lexp) = emit_labexp lexp       | emit_disp (I.ImmedLabel lexp) = emit_labexp lexp
266       | emit_disp _ = error "emit_disp"       | emit_disp _ = error "emit_disp"
267    
268  (*#line 212.7 "x86/x86.md"*)  (*#line 218.7 "x86/x86.md"*)
269     fun stupidGas (I.ImmedLabel lexp) = emit_labexp lexp     fun stupidGas (I.ImmedLabel lexp) = emit_labexp lexp
270       | stupidGas (I.LabelEA _) = error "stupidGas"       | stupidGas (I.LabelEA _) = error "stupidGas"
271       | stupidGas opnd = emit_operand opnd       | stupidGas opnd = emit_operand opnd
272    
273  (*#line 216.7 "x86/x86.md"*)  (*#line 223.7 "x86/x86.md"*)
274       fun isMemOpnd (I.MemReg _) = true
275         | isMemOpnd (I.FDirect f) = true
276         | isMemOpnd (I.LabelEA _) = true
277         | isMemOpnd (I.Displace _) = true
278         | isMemOpnd (I.Indexed _) = true
279         | isMemOpnd _ = false
280    
281    (*#line 229.7 "x86/x86.md"*)
282       fun showFbinOp (fbinOp, src) = emit (if (isMemOpnd src)
283              then fbinOp
284              else let
285    
286    (*#line 233.15 "x86/x86.md"*)
287                 val n = size fbinOp
288              in
289                 (
290                  case String.sub (fbinOp, n - 1) of
291                  (#"s" | #"t") => String.substring (fbinOp, 0, n - 1)
292                | _ => fbinOp
293                 )
294              end
295    )
296    
297    (*#line 239.7 "x86/x86.md"*)
298     val emit_dst = emit_operand     val emit_dst = emit_operand
299    
300  (*#line 217.7 "x86/x86.md"*)  (*#line 240.7 "x86/x86.md"*)
301     val emit_src = emit_operand     val emit_src = emit_operand
302    
303  (*#line 218.7 "x86/x86.md"*)  (*#line 241.7 "x86/x86.md"*)
304     val emit_opnd = emit_operand     val emit_opnd = emit_operand
305    
306  (*#line 219.7 "x86/x86.md"*)  (*#line 242.7 "x86/x86.md"*)
307     val emit_rsrc = emit_operand     val emit_rsrc = emit_operand
308    
309  (*#line 220.7 "x86/x86.md"*)  (*#line 243.7 "x86/x86.md"*)
310     val emit_lsrc = emit_operand     val emit_lsrc = emit_operand
311    
312  (*#line 221.7 "x86/x86.md"*)  (*#line 244.7 "x86/x86.md"*)
313     val emit_addr = emit_operand     val emit_addr = emit_operand
314    
315  (*#line 222.7 "x86/x86.md"*)  (*#line 245.7 "x86/x86.md"*)
316     val emit_src1 = emit_operand     val emit_src1 = emit_operand
317     fun emitInstr instr =     fun emitInstr instr =
318         ( tab ();         ( tab ();
# Line 424  Line 453 
453        | I.COPY{dst, src, tmp} => emitInstrs (Shuffle.shuffle {regmap=regmap, tmp=tmp, dst=dst, src=src})        | I.COPY{dst, src, tmp} => emitInstrs (Shuffle.shuffle {regmap=regmap, tmp=tmp, dst=dst, src=src})
454        | I.FCOPY{dst, src, tmp} => emitInstrs (Shuffle.shufflefp {regmap=regmap, tmp=tmp, dst=dst, src=src})        | I.FCOPY{dst, src, tmp} => emitInstrs (Shuffle.shufflefp {regmap=regmap, tmp=tmp, dst=dst, src=src})
455        | I.FBINARY{binOp, src, dst} =>        | I.FBINARY{binOp, src, dst} =>
456          ( emit_fbinOp binOp;          ( showFbinOp (asm_fbinOp binOp, src);
457          emit "\t";          emit "\t";
458          emit_src src;          emit_src src;
459          emit ", ";          emit ", ";
# Line 444  Line 473 
473        | I.FSTPS operand =>        | I.FSTPS operand =>
474          ( emit "fstps\t";          ( emit "fstps\t";
475          emit_operand operand )          emit_operand operand )
476          | I.FSTPT operand =>
477            ( emit "fstps\t";
478            emit_operand operand )
479        | I.FLDL operand =>        | I.FLDL operand =>
480          ( emit "fldl\t";          ( emit "fldl\t";
481          emit_operand operand )          emit_operand operand )
482        | I.FLDS operand =>        | I.FLDS operand =>
483          ( emit "flds\t";          ( emit "flds\t";
484          emit_operand operand )          emit_operand operand )
485          | I.FLDT operand =>
486            ( emit "fldt\t";
487            emit_operand operand )
488        | I.FILD operand =>        | I.FILD operand =>
489          ( emit "fild\t";          ( emit "fild\t";
490          emit_operand operand )          emit_operand operand )

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