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[smlnj] Log of /sml/trunk/src/MLRISC/x86/emit/x86MC.sml
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Revision 1009 - (view) (download) (annotate) - [select for diffs]
Modified Wed Jan 9 19:44:22 2002 UTC (17 years, 9 months ago) by george
File length: 11463 byte(s)
Diff to previous 1005
	Removed the native COPY and FCOPY instructions
	from all the architectures and replaced it with the
	explicit COPY instruction from the previous commit.

	It is now possible to simplify many of the optimizations
	modules that manipulate copies. This has not been
	done in this change.

Revision 1005 - (view) (download) (annotate) - [select for diffs]
Modified Sat Dec 8 07:24:04 2001 UTC (17 years, 10 months ago) by leunga
File length: 11686 byte(s)
Diff to previous 1003

    Updated peephole modules to match latest MLTREE and instruction
    representation.

Revision 1003 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 7 02:45:32 2001 UTC (17 years, 10 months ago) by george
File length: 11686 byte(s)
Diff to previous 984
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.

Revision 984 - (view) (download) (annotate) - [select for diffs]
Modified Wed Nov 21 19:00:08 2001 UTC (17 years, 11 months ago) by george
File length: 11492 byte(s)
Diff to previous 909
  Implemented a complete redesign of MLRISC pseudo-ops. Now there
  ought to never be any question of incompatabilities with
  pseudo-op syntax expected by host assemblers.

  For now, only modules supporting GAS syntax are implemented
  but more should follow, such as MASM, and vendor assembler
  syntax, e.g. IBM as, Sun as, etc.

Revision 909 - (view) (download) (annotate) - [select for diffs]
Modified Fri Aug 24 17:48:53 2001 UTC (18 years, 1 month ago) by george
File length: 11393 byte(s)
Diff to previous 900
removed clusters from MLRISC

Revision 900 - (view) (download) (annotate) - [select for diffs]
Modified Tue Aug 14 15:10:12 2001 UTC (18 years, 2 months ago) by jhr
File length: 11355 byte(s)
Diff to previous 839
  Moved CellSets from Cells to CellsBasis.

Revision 839 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jun 7 20:28:44 2001 UTC (18 years, 4 months ago) by blume
File length: 11283 byte(s)
Diff to previous 815
several internal changes related to C calls

Revision 815 - (view) (download) (annotate) - [select for diffs]
Modified Fri May 4 05:09:10 2001 UTC (18 years, 5 months ago) by leunga
File length: 11277 byte(s)
Diff to previous 797

    Moby related MLRISC changes

Revision 797 - (view) (download) (annotate) - [select for diffs]
Modified Fri Mar 16 00:00:17 2001 UTC (18 years, 7 months ago) by leunga
File length: 11039 byte(s)
Diff to previous 796

   x86 optimizations for x := x op y where x is a memory location.

Revision 796 - (view) (download) (annotate) - [select for diffs]
Modified Tue Mar 6 00:04:33 2001 UTC (18 years, 7 months ago) by leunga
File length: 10972 byte(s)
Diff to previous 775

   Support for alternative control-flow, exception handlers added.

Revision 775 - (view) (download) (annotate) - [select for diffs]
Modified Fri Jan 12 01:17:51 2001 UTC (18 years, 9 months ago) by leunga
File length: 10978 byte(s)
Diff to previous 744

    Merging the types labexp and mltree.
    tag leunga-20010111-labexp=mltree

Revision 744 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 8 04:11:42 2000 UTC (18 years, 10 months ago) by leunga
File length: 11014 byte(s)
Diff to previous 731

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

Revision 731 - (view) (download) (annotate) - [select for diffs]
Modified Fri Nov 10 22:57:45 2000 UTC (18 years, 11 months ago) by leunga
File length: 6587 byte(s)
Diff to previous 651

A new x86 floating point code generator.  By default it is off.
See HISTORY for details.   CVS tag=leunga-20001110-new-x86-fp

Revision 651 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jun 1 18:34:03 2000 UTC (19 years, 4 months ago) by monnier
File length: 6029 byte(s)
Diff to previous 646
bring revisions from the vendor branch to the trunk

Revision 646 - (view) (download) (annotate) - [select for diffs]
Modified Tue May 16 02:52:54 2000 UTC (19 years, 5 months ago) by leunga
File length: 6029 byte(s)
Diff to previous 624

  Slight cleanup on the Alpha.
  Added a bunch of instructions to the x86 instruction set.
  The module ra-rewrite-with-renaming has been improved.
  These should have no effect on SML/NJ.
  CVS tag=leunga-20000515-alpha-x86-ra

Revision 624 - (view) (download) (annotate) - [select for diffs]
Modified Fri Apr 21 03:06:21 2000 UTC (19 years, 6 months ago) by leunga
File length: 5967 byte(s)
Diff to previous 594

   This update synchronizes my repository with Yale's.  Most of these
changes are related to C--, Moby, and my optimizations.  It should have
little impact on SML/NJ.

   CVS tag leunga-20000420-ssa-c---stuff

Revision 594 - (view) (download) (annotate) - [select for diffs]
Modified Tue Apr 4 23:41:47 2000 UTC (19 years, 6 months ago) by leunga
File length: 5867 byte(s)
Diff to previous 583

      Changes to assembly output and fixes a bug in the x86 assembler
      CVS tag=leunga-20000404-x86-asm

Revision 583 - (view) (download) (annotate) - [select for diffs]
Modified Thu Mar 23 21:52:30 2000 UTC (19 years, 6 months ago) by leunga
File length: 5812 byte(s)
Diff to previous 555

1. X86 fixes/changes

   a.  The old code generated for SETcc was completely wrong.
       The Intel optimization guide is VERY misleading.

2. ALPHA fixes/changes

   a.  Added the instructions LDBU, LDWU, STB, STW as per Fermin's suggestion.
   b.  Added a new mode byteWordLoadStores to the functor parameter to Alpha()
   c.  Added reassociation code for address computation.

Revision 555 - (view) (download) (annotate) - [select for diffs]
Modified Fri Mar 3 16:10:30 2000 UTC (19 years, 7 months ago) by george
File length: 4673 byte(s)
Diff to previous 545
lal-20000303-new mltree -- take II

Revision 545 - (view) (download) (annotate) - [select for diffs]
Modified Thu Feb 24 13:56:44 2000 UTC (19 years, 7 months ago) by george
File length: 4573 byte(s)
Diff to previous 470
  Changes to MLTREE

Revision 470 - (view) (download) (annotate) - [select for diffs]
Modified Wed Nov 10 22:42:52 1999 UTC (19 years, 11 months ago) by monnier
File length: 3800 byte(s)
Copied from: sml/branches/SMLNJ/src/MLRISC/x86/emit/x86MC.sml revision 469
Diff to previous 469
This commit was generated by cvs2svn to compensate for changes in r469,
which included commits to RCS files with non-trunk default branches.

Revision 469 - (view) (download) (annotate) - [select for diffs]
Modified Wed Nov 10 22:42:52 1999 UTC (19 years, 11 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/x86/emit/x86MC.sml
File length: 3800 byte(s)
Diff to previous 429
version 110.23

Revision 429 - (view) (download) (annotate) - [select for diffs]
Modified Wed Sep 8 09:47:00 1999 UTC (20 years, 1 month ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/x86/emit/x86MC.sml
File length: 3837 byte(s)
Diff to previous 411
version 110.21

Revision 411 - (view) (download) (annotate) - [select for diffs]
Modified Fri Sep 3 00:25:03 1999 UTC (20 years, 1 month ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/x86/emit/x86MC.sml
File length: 12438 byte(s)
Diff to previous 247
version 110.19

Revision 247 - (view) (download) (annotate) - [select for diffs]
Added Sat Apr 17 18:47:13 1999 UTC (20 years, 6 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/x86/emit/x86MC.sml
File length: 12399 byte(s)
version 110.16

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