Home My Page Projects Code Snippets Project Openings SML/NJ
Summary Activity Forums Tracker Lists Tasks Docs Surveys News SCM Files

SCM Repository

[smlnj] Log of /sml/trunk/src/MLRISC/x86/instructions/x86Shuffle.sml
[smlnj] / sml / trunk / src / MLRISC / x86 / instructions / x86Shuffle.sml  
ViewVC logotype

Log of /sml/trunk/src/MLRISC/x86/instructions/x86Shuffle.sml

Parent Directory Parent Directory


Sticky Revision:
(Current path doesn't exist after revision 2125)

Revision 1009 - (view) (download) (annotate) - [select for diffs]
Modified Wed Jan 9 19:44:22 2002 UTC (17 years, 11 months ago) by george
File length: 4890 byte(s)
Diff to previous 1003
	Removed the native COPY and FCOPY instructions
	from all the architectures and replaced it with the
	explicit COPY instruction from the previous commit.

	It is now possible to simplify many of the optimizations
	modules that manipulate copies. This has not been
	done in this change.

Revision 1003 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 7 02:45:32 2001 UTC (18 years ago) by george
File length: 4869 byte(s)
Diff to previous 889
Changed the representation of instructions from being fully abstract
to being partially concrete. That is to say:

  from
	type instruction

  to
	type instr				(* machine instruction *)

	datatype instruction =
	    LIVE of {regs: C.cellset, spilled: C.cellset}
          | KILL of {regs: C.cellset, spilled: C.cellset}
          | COPYXXX of {k: CB.cellkind, dst: CB.cell list, src: CB.cell list}
          | ANNOTATION of {i: instruction, a: Annotations.annotation}
          | INSTR of instr

This makes the handling of certain special instructions that appear on
all architectures easier and uniform.

LIVE and KILL say that a list of registers are live or killed at the
program point where they appear. No spill code is generated when an
element of the 'regs' field is spilled, but the register is moved to
the 'spilled' (which is present, more for debugging than anything else).

LIVE replaces the (now deprecated) DEFFREG instruction on the alpha.
We used to generate:

	DEFFREG f1
	f1 := f2 + f3
        trapb

but now generate:

	f1 := f2 + f3
	trapb
	LIVE {regs=[f1,f2,f3], spilled=[]}

Furthermore, the DEFFREG (hack) required that all floating point instruction
use all registers mentioned in the instruction. Therefore f1 := f2 + f3,
defines f1 and uses [f1,f2,f3]! This hack is no longer required resulting
in a cleaner alpha implementation. (Hopefully, intel will not get rid of
this architecture).

COPYXXX is intended to replace the parallel COPY and FCOPY  available on
all the architectures. This will result in further simplification of the
register allocator that must be aware of them for coalescing purposes, and
will also simplify certain aspects of the machine description that provides
callbacks related to parallel copies.

ANNOTATION should be obvious, and now INSTR represents the honest to God
machine instruction set!

The <arch>/instructions/<arch>Instr.sml files define certain utility
functions for making porting easier -- essentially converting upper case
to lower case. All machine instructions (of type instr) are in upper case,
and the lower case form generates an MLRISC instruction. For example on
the alpha we have:

  datatype instr =
     LDA of {r:cell, b:cell, d:operand}
   | ...

  val lda : {r:cell, b:cell, d:operand} -> instruction
    ...

where lda is just (INSTR o LDA), etc.

Revision 889 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jul 19 20:35:20 2001 UTC (18 years, 4 months ago) by george
File length: 4922 byte(s)
Diff to previous 797
Substantial simplification in the CELLS interface

Revision 797 - (view) (download) (annotate) - [select for diffs]
Modified Fri Mar 16 00:00:17 2001 UTC (18 years, 9 months ago) by leunga
File length: 4891 byte(s)
Diff to previous 744

   x86 optimizations for x := x op y where x is a memory location.

Revision 744 - (view) (download) (annotate) - [select for diffs]
Modified Fri Dec 8 04:11:42 2000 UTC (19 years ago) by leunga
File length: 1643 byte(s)
Diff to previous 731

   A CVS update record!

   Changed type cell from int to datatype, and numerous other changes.
   Affect every client of MLRISC.  Lal says this can be bootstrapped on all
   machines.  See smlnj/HISTORY for details.

   Tag:  leunga-20001207-cell-monster-hack

Revision 731 - (view) (download) (annotate) - [select for diffs]
Modified Fri Nov 10 22:57:45 2000 UTC (19 years, 1 month ago) by leunga
File length: 1743 byte(s)
Diff to previous 651

A new x86 floating point code generator.  By default it is off.
See HISTORY for details.   CVS tag=leunga-20001110-new-x86-fp

Revision 651 - (view) (download) (annotate) - [select for diffs]
Modified Thu Jun 1 18:34:03 2000 UTC (19 years, 6 months ago) by monnier
File length: 1212 byte(s)
Diff to previous 585
bring revisions from the vendor branch to the trunk

Revision 585 - (view) (download) (annotate) - [select for diffs]
Modified Wed Mar 29 23:55:35 2000 UTC (19 years, 8 months ago) by leunga
File length: 1212 byte(s)
Diff to previous 545

   This update contains major changes to the code generator and various
back ends.  Please see the entry leunga-20000327-mlriscGen_hppa_alpha_x86
in the file sml/HISTORY for details.

Revision 545 - (view) (download) (annotate) - [select for diffs]
Modified Thu Feb 24 13:56:44 2000 UTC (19 years, 9 months ago) by george
File length: 513 byte(s)
Diff to previous 412
  Changes to MLTREE

Revision 412 - (view) (download) (annotate) - [select for diffs]
Modified Fri Sep 3 00:25:03 1999 UTC (20 years, 3 months ago) by monnier
File length: 444 byte(s)
Copied from: sml/branches/SMLNJ/src/MLRISC/x86/instructions/x86Shuffle.sml revision 411
Diff to previous 411
This commit was generated by cvs2svn to compensate for changes in r411,
which included commits to RCS files with non-trunk default branches.

Revision 411 - (view) (download) (annotate) - [select for diffs]
Modified Fri Sep 3 00:25:03 1999 UTC (20 years, 3 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/x86/instructions/x86Shuffle.sml
File length: 444 byte(s)
Diff to previous 247
version 110.19

Revision 247 - (view) (download) (annotate) - [select for diffs]
Added Sat Apr 17 18:47:13 1999 UTC (20 years, 8 months ago) by monnier
Original Path: sml/branches/SMLNJ/src/MLRISC/x86/instructions/x86Shuffle.sml
File length: 445 byte(s)
version 110.16

This form allows you to request diffs between any two revisions of this file. For each of the two "sides" of the diff, enter a numeric revision.

  Diffs between and
  Type of Diff should be a

Sort log by:

root@smlnj-gforge.cs.uchicago.edu
ViewVC Help
Powered by ViewVC 1.0.0