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[smlnj] Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml
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Annotation of /sml/trunk/src/MLRISC/x86/mltree/x86.sml

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1 : leunga 583 (*
2 : monnier 247 *
3 :     * COPYRIGHT (c) 1998 Bell Laboratories.
4 : george 545 *
5 :     * This is a revised version that takes into account of
6 :     * the extended x86 instruction set, and has better handling of
7 :     * non-standard types. I've factored out the integer/floating point
8 :     * comparison code, added optimizations for conditional moves.
9 :     * The latter generates SETcc and CMOVcc (Pentium Pro only) instructions.
10 :     * To avoid problems, I have tried to incorporate as much of
11 :     * Lal's original magic incantations as possible.
12 : monnier 247 *
13 : george 545 * Some changes:
14 :     *
15 :     * 1. REMU/REMS/REMT are now supported
16 :     * 2. COND is supported by generating SETcc and/or CMOVcc; this
17 :     * may require at least a Pentium II to work.
18 :     * 3. Division by a constant has been optimized. Division by
19 :     * a power of 2 generates SHRL or SARL.
20 :     * 4. Better addressing mode selection has been implemented. This should
21 :     * improve array indexing on SML/NJ.
22 :     * 5. Generate testl/testb instead of andl whenever appropriate. This
23 :     * is recommended by the Intel Optimization Guide and seems to improve
24 :     * boxity tests on SML/NJ.
25 : leunga 731 *
26 :     * More changes for floating point:
27 :     * A new mode is implemented which generates pseudo 3-address instructions
28 :     * for floating point. These instructions are register allocated the
29 :     * normal way, with the virtual registers mapped onto a set of pseudo
30 :     * %fp registers. These registers are then mapped onto the %st registers
31 :     * with a new postprocessing phase.
32 :     *
33 : george 545 * -- Allen
34 : monnier 247 *)
35 : george 545 local
36 :     val rewriteMemReg = true (* should we rewrite memRegs *)
37 : leunga 731 val enableFastFPMode = true (* set this to false to disable the mode *)
38 : george 545 in
39 :    
40 : monnier 247 functor X86
41 :     (structure X86Instr : X86INSTR
42 : leunga 797 structure MLTreeUtils : MLTREE_UTILS
43 : george 933 where T = X86Instr.T
44 : george 555 structure ExtensionComp : MLTREE_EXTENSION_COMP
45 : george 933 where I = X86Instr and T = X86Instr.T
46 : george 984 structure MLTreeStream : MLTREE_STREAM
47 :     where T = ExtensionComp.T
48 : george 545 datatype arch = Pentium | PentiumPro | PentiumII | PentiumIII
49 :     val arch : arch ref
50 : leunga 593 val cvti2f :
51 : leunga 815 {ty: X86Instr.T.ty,
52 :     src: X86Instr.operand,
53 :     (* source operand, guaranteed to be non-memory! *)
54 :     an: Annotations.annotations ref (* cluster annotations *)
55 :     } ->
56 : leunga 593 {instrs : X86Instr.instruction list,(* the instructions *)
57 :     tempMem: X86Instr.operand, (* temporary for CVTI2F *)
58 :     cleanup: X86Instr.instruction list (* cleanup code *)
59 :     }
60 : leunga 731 (* When the following flag is set, we allocate floating point registers
61 :     * directly on the floating point stack
62 :     *)
63 :     val fast_floating_point : bool ref
64 : george 545 ) : sig include MLTREECOMP
65 :     val rewriteMemReg : bool
66 :     end =
67 : monnier 247 struct
68 : leunga 775 structure I = X86Instr
69 :     structure T = I.T
70 : george 984 structure TS = ExtensionComp.TS
71 : george 545 structure C = I.C
72 :     structure Shuffle = Shuffle(I)
73 : monnier 247 structure W32 = Word32
74 : george 545 structure A = MLRiscAnnotations
75 : george 909 structure CFG = ExtensionComp.CFG
76 : george 889 structure CB = CellsBasis
77 : monnier 247
78 : george 984 type instrStream = (I.instruction,C.cellset,CFG.cfg) TS.stream
79 :     type mltreeStream = (T.stm,T.mlrisc list,CFG.cfg) TS.stream
80 : leunga 565
81 :     datatype kind = REAL | INTEGER
82 : george 545
83 :     structure Gen = MLTreeGen
84 :     (structure T = T
85 :     val intTy = 32
86 :     val naturalWidths = [32]
87 :     datatype rep = SE | ZE | NEITHER
88 :     val rep = NEITHER
89 :     )
90 :    
91 : monnier 411 fun error msg = MLRiscErrorMsg.error("X86",msg)
92 : monnier 247
93 : george 545 (* Should we perform automatic MemReg translation?
94 :     * If this is on, we can avoid doing RewritePseudo phase entirely.
95 :     *)
96 :     val rewriteMemReg = rewriteMemReg
97 : leunga 731
98 :     (* The following hardcoded *)
99 : leunga 744 fun isMemReg r = rewriteMemReg andalso
100 : george 889 let val r = CB.registerNum r
101 : leunga 744 in r >= 8 andalso r < 32
102 :     end
103 : leunga 731 fun isFMemReg r = if enableFastFPMode andalso !fast_floating_point
104 : george 889 then let val r = CB.registerNum r
105 : leunga 744 in r >= 8 andalso r < 32 end
106 : leunga 731 else true
107 : leunga 744 val isAnyFMemReg = List.exists (fn r =>
108 : george 889 let val r = CB.registerNum r
109 : leunga 744 in r >= 8 andalso r < 32 end
110 :     )
111 : monnier 247
112 : george 555 val ST0 = C.ST 0
113 :     val ST7 = C.ST 7
114 : leunga 797 val one = T.I.int_1
115 : george 555
116 : leunga 797 val opcodes8 = {INC=I.INCB,DEC=I.DECB,ADD=I.ADDB,SUB=I.SUBB,
117 :     NOT=I.NOTB,NEG=I.NEGB,
118 :     SHL=I.SHLB,SHR=I.SHRB,SAR=I.SARB,
119 :     OR=I.ORB,AND=I.ANDB,XOR=I.XORB}
120 :     val opcodes16 = {INC=I.INCW,DEC=I.DECW,ADD=I.ADDW,SUB=I.SUBW,
121 :     NOT=I.NOTW,NEG=I.NEGW,
122 :     SHL=I.SHLW,SHR=I.SHRW,SAR=I.SARW,
123 :     OR=I.ORW,AND=I.ANDW,XOR=I.XORW}
124 :     val opcodes32 = {INC=I.INCL,DEC=I.DECL,ADD=I.ADDL,SUB=I.SUBL,
125 :     NOT=I.NOTL,NEG=I.NEGL,
126 :     SHL=I.SHLL,SHR=I.SHRL,SAR=I.SARL,
127 :     OR=I.ORL,AND=I.ANDL,XOR=I.XORL}
128 :    
129 : george 545 (*
130 :     * The code generator
131 :     *)
132 : monnier 411 fun selectInstructions
133 : george 545 (instrStream as
134 : george 1003 TS.S.STREAM{emit=emitInstruction,defineLabel,entryLabel,pseudoOp,
135 :     annotation,getAnnotations,beginCluster,endCluster,exitBlock,comment,...}) =
136 :     let
137 :     val emit = emitInstruction o I.INSTR
138 :     exception EA
139 : monnier 411
140 : george 545 (* label where a trap is generated -- one per cluster *)
141 :     val trapLabel = ref (NONE: (I.instruction * Label.label) option)
142 : monnier 247
143 : leunga 731 (* flag floating point generation *)
144 :     val floatingPointUsed = ref false
145 :    
146 : george 545 (* effective address of an integer register *)
147 : leunga 731 fun IntReg r = if isMemReg r then I.MemReg r else I.Direct r
148 :     and RealReg r = if isFMemReg r then I.FDirect r else I.FPR r
149 : monnier 411
150 : george 545 (* Add an overflow trap *)
151 :     fun trap() =
152 :     let val jmp =
153 :     case !trapLabel of
154 : george 909 NONE => let val label = Label.label "trap" ()
155 : george 1003 val jmp = I.jcc{cond=I.O,
156 : leunga 775 opnd=I.ImmedLabel(T.LABEL label)}
157 : george 545 in trapLabel := SOME(jmp, label); jmp end
158 :     | SOME(jmp, _) => jmp
159 : george 1003 in emitInstruction jmp end
160 : monnier 411
161 : george 545 val newReg = C.newReg
162 :     val newFreg = C.newFreg
163 : monnier 247
164 : leunga 731 fun fsize 32 = I.FP32
165 :     | fsize 64 = I.FP64
166 :     | fsize 80 = I.FP80
167 :     | fsize _ = error "fsize"
168 :    
169 : george 545 (* mark an expression with a list of annotations *)
170 : george 1009 fun mark'(i,[]) = emitInstruction(i)
171 : george 545 | mark'(i,a::an) = mark'(I.ANNOTATION{i=i,a=a},an)
172 : monnier 247
173 : george 545 (* annotate an expression and emit it *)
174 : george 1009 fun mark(i,an) = mark'(I.INSTR i,an)
175 : monnier 247
176 : george 1003 val emits = app emitInstruction
177 : leunga 731
178 : george 545 (* emit parallel copies for integers
179 :     * Translates parallel copies that involve memregs into
180 :     * individual copies.
181 :     *)
182 :     fun copy([], [], an) = ()
183 :     | copy(dst, src, an) =
184 :     let fun mvInstr{dst as I.MemReg rd, src as I.MemReg rs} =
185 : george 889 if CB.sameColor(rd,rs) then [] else
186 : george 545 let val tmpR = I.Direct(newReg())
187 : george 1003 in [I.move{mvOp=I.MOVL, src=src, dst=tmpR},
188 :     I.move{mvOp=I.MOVL, src=tmpR, dst=dst}]
189 : george 545 end
190 :     | mvInstr{dst=I.Direct rd, src=I.Direct rs} =
191 : george 889 if CB.sameColor(rd,rs) then []
192 : george 1009 else [I.COPY{k=CB.GP, sz=32, dst=[rd], src=[rs], tmp=NONE}]
193 : george 1003 | mvInstr{dst, src} = [I.move{mvOp=I.MOVL, src=src, dst=dst}]
194 : george 545 in
195 : leunga 731 emits (Shuffle.shuffle{mvInstr=mvInstr, ea=IntReg}
196 : leunga 744 {tmp=SOME(I.Direct(newReg())),
197 : george 545 dst=dst, src=src})
198 :     end
199 :    
200 :     (* conversions *)
201 :     val itow = Word.fromInt
202 :     val wtoi = Word.toInt
203 : george 761 fun toInt32 i = T.I.toInt32(32, i)
204 : george 545 val w32toi32 = Word32.toLargeIntX
205 :     val i32tow32 = Word32.fromLargeInt
206 : monnier 247
207 : george 545 (* One day, this is going to bite us when precision(LargeInt)>32 *)
208 :     fun wToInt32 w = Int32.fromLarge(Word32.toLargeIntX w)
209 : monnier 247
210 : george 545 (* some useful registers *)
211 :     val eax = I.Direct(C.eax)
212 :     val ecx = I.Direct(C.ecx)
213 :     val edx = I.Direct(C.edx)
214 : monnier 247
215 : leunga 775 fun immedLabel lab = I.ImmedLabel(T.LABEL lab)
216 : george 545
217 :     (* Is the expression zero? *)
218 : george 761 fun isZero(T.LI z) = T.I.isZero z
219 : george 545 | isZero(T.MARK(e,a)) = isZero e
220 :     | isZero _ = false
221 :     (* Does the expression set the zero bit?
222 :     * WARNING: we assume these things are not optimized out!
223 :     *)
224 :     fun setZeroBit(T.ANDB _) = true
225 :     | setZeroBit(T.ORB _) = true
226 :     | setZeroBit(T.XORB _) = true
227 :     | setZeroBit(T.SRA _) = true
228 :     | setZeroBit(T.SRL _) = true
229 :     | setZeroBit(T.SLL _) = true
230 : leunga 695 | setZeroBit(T.SUB _) = true
231 :     | setZeroBit(T.ADDT _) = true
232 :     | setZeroBit(T.SUBT _) = true
233 : george 545 | setZeroBit(T.MARK(e, _)) = setZeroBit e
234 :     | setZeroBit _ = false
235 : monnier 247
236 : leunga 695 fun setZeroBit2(T.ANDB _) = true
237 :     | setZeroBit2(T.ORB _) = true
238 :     | setZeroBit2(T.XORB _) = true
239 :     | setZeroBit2(T.SRA _) = true
240 :     | setZeroBit2(T.SRL _) = true
241 :     | setZeroBit2(T.SLL _) = true
242 :     | setZeroBit2(T.ADD(32, _, _)) = true (* can't use leal! *)
243 :     | setZeroBit2(T.SUB _) = true
244 :     | setZeroBit2(T.ADDT _) = true
245 :     | setZeroBit2(T.SUBT _) = true
246 :     | setZeroBit2(T.MARK(e, _)) = setZeroBit2 e
247 :     | setZeroBit2 _ = false
248 :    
249 : leunga 731 (* emit parallel copies for floating point
250 :     * Normal version.
251 :     *)
252 :     fun fcopy'(fty, [], [], _) = ()
253 :     | fcopy'(fty, dst as [_], src as [_], an) =
254 : george 1009 mark'(I.COPY{k=CB.FP, sz=fty, dst=dst,src=src,tmp=NONE}, an)
255 : leunga 731 | fcopy'(fty, dst, src, an) =
256 : george 1009 mark'(I.COPY{k=CB.FP, sz=fty, dst=dst,src=src,tmp=SOME(I.FDirect(newFreg()))}, an)
257 : monnier 247
258 : leunga 731 (* emit parallel copies for floating point.
259 :     * Fast version.
260 :     * Translates parallel copies that involve memregs into
261 :     * individual copies.
262 :     *)
263 :    
264 :     fun fcopy''(fty, [], [], _) = ()
265 :     | fcopy''(fty, dst, src, an) =
266 :     if true orelse isAnyFMemReg dst orelse isAnyFMemReg src then
267 :     let val fsize = fsize fty
268 : george 1003 fun mvInstr{dst, src} = [I.fmove{fsize=fsize, src=src, dst=dst}]
269 : leunga 731 in
270 :     emits (Shuffle.shuffle{mvInstr=mvInstr, ea=RealReg}
271 : leunga 744 {tmp=case dst of
272 : leunga 731 [_] => NONE
273 :     | _ => SOME(I.FPR(newReg())),
274 :     dst=dst, src=src})
275 :     end
276 :     else
277 : george 1009 mark'(I.COPY{k=CB.FP, sz=fty, dst=dst,
278 :     src=src,tmp=
279 : leunga 731 case dst of
280 :     [_] => NONE
281 :     | _ => SOME(I.FPR(newFreg()))}, an)
282 :    
283 :     fun fcopy x = if enableFastFPMode andalso !fast_floating_point
284 :     then fcopy'' x else fcopy' x
285 :    
286 : george 545 (* Translates MLTREE condition code to x86 condition code *)
287 :     fun cond T.LT = I.LT | cond T.LTU = I.B
288 :     | cond T.LE = I.LE | cond T.LEU = I.BE
289 :     | cond T.EQ = I.EQ | cond T.NE = I.NE
290 :     | cond T.GE = I.GE | cond T.GEU = I.AE
291 :     | cond T.GT = I.GT | cond T.GTU = I.A
292 : monnier 247
293 : leunga 815 fun zero dst = emit(I.BINARY{binOp=I.XORL, src=dst, dst=dst})
294 :    
295 : george 545 (* Move and annotate *)
296 :     fun move'(src as I.Direct s, dst as I.Direct d, an) =
297 : george 889 if CB.sameColor(s,d) then ()
298 : george 1009 else mark'(I.COPY{k=CB.GP, sz=32, dst=[d], src=[s], tmp=NONE}, an)
299 : leunga 815 | move'(I.Immed 0, dst as I.Direct d, an) =
300 :     mark(I.BINARY{binOp=I.XORL, src=dst, dst=dst}, an)
301 : george 545 | move'(src, dst, an) = mark(I.MOVE{mvOp=I.MOVL, src=src, dst=dst}, an)
302 : monnier 247
303 : george 545 (* Move only! *)
304 :     fun move(src, dst) = move'(src, dst, [])
305 : monnier 247
306 : george 545 val readonly = I.Region.readonly
307 : monnier 247
308 : george 545 (*
309 : george 761 * Compute an effective address.
310 : george 545 *)
311 : george 761 fun address(ea, mem) = let
312 : george 545 (* Keep building a bigger and bigger effective address expressions
313 :     * The input is a list of trees
314 :     * b -- base
315 :     * i -- index
316 :     * s -- scale
317 :     * d -- immed displacement
318 :     *)
319 :     fun doEA([], b, i, s, d) = makeAddressingMode(b, i, s, d)
320 :     | doEA(t::trees, b, i, s, d) =
321 :     (case t of
322 : george 761 T.LI n => doEAImmed(trees, toInt32 n, b, i, s, d)
323 : leunga 775 | T.CONST _ => doEALabel(trees, t, b, i, s, d)
324 :     | T.LABEL _ => doEALabel(trees, t, b, i, s, d)
325 :     | T.LABEXP le => doEALabel(trees, le, b, i, s, d)
326 : george 545 | T.ADD(32, t1, t2 as T.REG(_,r)) =>
327 :     if isMemReg r then doEA(t2::t1::trees, b, i, s, d)
328 :     else doEA(t1::t2::trees, b, i, s, d)
329 :     | T.ADD(32, t1, t2) => doEA(t1::t2::trees, b, i, s, d)
330 :     | T.SUB(32, t1, T.LI n) =>
331 : george 761 doEA(t1::T.LI(T.I.NEG(32,n))::trees, b, i, s, d)
332 :     | T.SLL(32, t1, T.LI n) => let
333 :     val n = T.I.toInt(32, n)
334 :     in
335 :     case n
336 :     of 0 => displace(trees, t1, b, i, s, d)
337 :     | 1 => indexed(trees, t1, t, 1, b, i, s, d)
338 :     | 2 => indexed(trees, t1, t, 2, b, i, s, d)
339 :     | 3 => indexed(trees, t1, t, 3, b, i, s, d)
340 :     | _ => displace(trees, t, b, i, s, d)
341 :     end
342 : george 545 | t => displace(trees, t, b, i, s, d)
343 :     )
344 : monnier 247
345 : george 545 (* Add an immed constant *)
346 :     and doEAImmed(trees, 0, b, i, s, d) = doEA(trees, b, i, s, d)
347 :     | doEAImmed(trees, n, b, i, s, I.Immed m) =
348 : george 761 doEA(trees, b, i, s, I.Immed(n+m))
349 : george 545 | doEAImmed(trees, n, b, i, s, I.ImmedLabel le) =
350 : leunga 775 doEA(trees, b, i, s,
351 :     I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, n)))))
352 : george 545 | doEAImmed(trees, n, b, i, s, _) = error "doEAImmed"
353 : monnier 247
354 : george 545 (* Add a label expression *)
355 :     and doEALabel(trees, le, b, i, s, I.Immed 0) =
356 :     doEA(trees, b, i, s, I.ImmedLabel le)
357 :     | doEALabel(trees, le, b, i, s, I.Immed m) =
358 :     doEA(trees, b, i, s,
359 : leunga 775 I.ImmedLabel(T.ADD(32,le,T.LI(T.I.fromInt32(32, m))))
360 : george 545 handle Overflow => error "doEALabel: constant too large")
361 :     | doEALabel(trees, le, b, i, s, I.ImmedLabel le') =
362 : leunga 775 doEA(trees, b, i, s, I.ImmedLabel(T.ADD(32,le,le')))
363 : george 545 | doEALabel(trees, le, b, i, s, _) = error "doEALabel"
364 : monnier 247
365 : george 545 and makeAddressingMode(NONE, NONE, _, disp) = disp
366 :     | makeAddressingMode(SOME base, NONE, _, disp) =
367 :     I.Displace{base=base, disp=disp, mem=mem}
368 :     | makeAddressingMode(base, SOME index, scale, disp) =
369 : george 761 I.Indexed{base=base, index=index, scale=scale,
370 : george 545 disp=disp, mem=mem}
371 : monnier 247
372 : george 545 (* generate code for tree and ensure that it is not in %esp *)
373 :     and exprNotEsp tree =
374 :     let val r = expr tree
375 : george 889 in if CB.sameColor(r, C.esp) then
376 : george 545 let val tmp = newReg()
377 :     in move(I.Direct r, I.Direct tmp); tmp end
378 :     else r
379 :     end
380 : monnier 247
381 : george 545 (* Add a base register *)
382 :     and displace(trees, t, NONE, i, s, d) = (* no base yet *)
383 :     doEA(trees, SOME(expr t), i, s, d)
384 :     | displace(trees, t, b as SOME base, NONE, _, d) = (* no index *)
385 :     (* make t the index, but make sure that it is not %esp! *)
386 :     let val i = expr t
387 : george 889 in if CB.sameColor(i, C.esp) then
388 : george 545 (* swap base and index *)
389 : george 889 if CB.sameColor(base, C.esp) then
390 : george 545 doEA(trees, SOME i, b, 0, d)
391 :     else (* base and index = %esp! *)
392 :     let val index = newReg()
393 :     in move(I.Direct i, I.Direct index);
394 :     doEA(trees, b, SOME index, 0, d)
395 :     end
396 :     else
397 :     doEA(trees, b, SOME i, 0, d)
398 :     end
399 :     | displace(trees, t, SOME base, i, s, d) = (* base and index *)
400 :     let val b = expr(T.ADD(32,T.REG(32,base),t))
401 :     in doEA(trees, SOME b, i, s, d) end
402 : monnier 247
403 : george 545 (* Add an indexed register *)
404 :     and indexed(trees, t, t0, scale, b, NONE, _, d) = (* no index yet *)
405 :     doEA(trees, b, SOME(exprNotEsp t), scale, d)
406 :     | indexed(trees, _, t0, _, NONE, i, s, d) = (* no base *)
407 :     doEA(trees, SOME(expr t0), i, s, d)
408 :     | indexed(trees, _, t0, _, SOME base, i, s, d) = (*base and index*)
409 :     let val b = expr(T.ADD(32, t0, T.REG(32, base)))
410 :     in doEA(trees, SOME b, i, s, d) end
411 :    
412 :     in case doEA([ea], NONE, NONE, 0, I.Immed 0) of
413 :     I.Immed _ => raise EA
414 :     | I.ImmedLabel le => I.LabelEA le
415 :     | ea => ea
416 :     end (* address *)
417 : monnier 247
418 : george 545 (* reduce an expression into an operand *)
419 : george 761 and operand(T.LI i) = I.Immed(toInt32(i))
420 : leunga 775 | operand(x as (T.CONST _ | T.LABEL _)) = I.ImmedLabel x
421 :     | operand(T.LABEXP le) = I.ImmedLabel le
422 : george 545 | operand(T.REG(_,r)) = IntReg r
423 :     | operand(T.LOAD(32,ea,mem)) = address(ea, mem)
424 :     | operand(t) = I.Direct(expr t)
425 : monnier 247
426 : george 545 and moveToReg(opnd) =
427 :     let val dst = I.Direct(newReg())
428 :     in move(opnd, dst); dst
429 :     end
430 : monnier 247
431 : george 545 and reduceOpnd(I.Direct r) = r
432 :     | reduceOpnd opnd =
433 :     let val dst = newReg()
434 :     in move(opnd, I.Direct dst); dst
435 :     end
436 : monnier 247
437 : george 545 (* ensure that the operand is either an immed or register *)
438 :     and immedOrReg(opnd as I.Displace _) = moveToReg opnd
439 :     | immedOrReg(opnd as I.Indexed _) = moveToReg opnd
440 :     | immedOrReg(opnd as I.MemReg _) = moveToReg opnd
441 :     | immedOrReg(opnd as I.LabelEA _) = moveToReg opnd
442 :     | immedOrReg opnd = opnd
443 : monnier 247
444 : george 545 and isImmediate(I.Immed _) = true
445 :     | isImmediate(I.ImmedLabel _) = true
446 :     | isImmediate _ = false
447 : monnier 247
448 : george 545 and regOrMem opnd = if isImmediate opnd then moveToReg opnd else opnd
449 :    
450 :     and isMemOpnd opnd =
451 :     (case opnd of
452 :     I.Displace _ => true
453 :     | I.Indexed _ => true
454 :     | I.MemReg _ => true
455 :     | I.LabelEA _ => true
456 : george 555 | I.FDirect f => true
457 : george 545 | _ => false
458 :     )
459 :    
460 :     (*
461 :     * Compute an integer expression and put the result in
462 :     * the destination register rd.
463 :     *)
464 : george 889 and doExpr(exp, rd : CB.cell, an) =
465 : george 545 let val rdOpnd = IntReg rd
466 : monnier 247
467 : george 889 fun equalRd(I.Direct r) = CB.sameColor(r, rd)
468 :     | equalRd(I.MemReg r) = CB.sameColor(r, rd)
469 : george 545 | equalRd _ = false
470 : monnier 247
471 : george 545 (* Emit a binary operator. If the destination is
472 :     * a memReg, do something smarter.
473 :     *)
474 :     fun genBinary(binOp, opnd1, opnd2) =
475 :     if isMemReg rd andalso
476 :     (isMemOpnd opnd1 orelse isMemOpnd opnd2) orelse
477 :     equalRd(opnd2)
478 :     then
479 :     let val tmpR = newReg()
480 :     val tmp = I.Direct tmpR
481 :     in move(opnd1, tmp);
482 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=tmp}, an);
483 :     move(tmp, rdOpnd)
484 :     end
485 :     else
486 :     (move(opnd1, rdOpnd);
487 :     mark(I.BINARY{binOp=binOp, src=opnd2, dst=rdOpnd}, an)
488 :     )
489 : monnier 247
490 : george 545 (* Generate a binary operator; it may commute *)
491 :     fun binaryComm(binOp, e1, e2) =
492 :     let val (opnd1, opnd2) =
493 :     case (operand e1, operand e2) of
494 :     (x as I.Immed _, y) => (y, x)
495 :     | (x as I.ImmedLabel _, y) => (y, x)
496 :     | (x, y as I.Direct _) => (y, x)
497 :     | (x, y) => (x, y)
498 :     in genBinary(binOp, opnd1, opnd2)
499 :     end
500 :    
501 :     (* Generate a binary operator; non-commutative *)
502 :     fun binary(binOp, e1, e2) =
503 :     genBinary(binOp, operand e1, operand e2)
504 :    
505 :     (* Generate a unary operator *)
506 :     fun unary(unOp, e) =
507 :     let val opnd = operand e
508 :     in if isMemReg rd andalso isMemOpnd opnd then
509 :     let val tmp = I.Direct(newReg())
510 :     in move(opnd, tmp); move(tmp, rdOpnd)
511 :     end
512 :     else move(opnd, rdOpnd);
513 :     mark(I.UNARY{unOp=unOp, opnd=rdOpnd}, an)
514 :     end
515 :    
516 :     (* Generate shifts; the shift
517 :     * amount must be a constant or in %ecx *)
518 :     fun shift(opcode, e1, e2) =
519 :     let val (opnd1, opnd2) = (operand e1, operand e2)
520 :     in case opnd2 of
521 :     I.Immed _ => genBinary(opcode, opnd1, opnd2)
522 :     | _ =>
523 :     if equalRd(opnd2) then
524 :     let val tmpR = newReg()
525 :     val tmp = I.Direct tmpR
526 :     in move(opnd1, tmp);
527 :     move(opnd2, ecx);
528 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=tmp},an);
529 :     move(tmp, rdOpnd)
530 :     end
531 :     else
532 :     (move(opnd1, rdOpnd);
533 :     move(opnd2, ecx);
534 :     mark(I.BINARY{binOp=opcode, src=ecx, dst=rdOpnd},an)
535 :     )
536 :     end
537 :    
538 :     (* Division or remainder: divisor must be in %edx:%eax pair *)
539 :     fun divrem(signed, overflow, e1, e2, resultReg) =
540 :     let val (opnd1, opnd2) = (operand e1, operand e2)
541 :     val _ = move(opnd1, eax)
542 : leunga 815 val oper = if signed then (emit(I.CDQ); I.IDIVL1)
543 :     else (zero edx; I.DIVL1)
544 : george 545 in mark(I.MULTDIV{multDivOp=oper, src=regOrMem opnd2},an);
545 :     move(resultReg, rdOpnd);
546 :     if overflow then trap() else ()
547 :     end
548 :    
549 :     (* Optimize the special case for division *)
550 : george 761 fun divide(signed, overflow, e1, e2 as T.LI n') = let
551 :     val n = toInt32 n'
552 :     val w = T.I.toWord32(32, n')
553 :     fun isPowerOf2 w = W32.andb((w - 0w1), w) = 0w0
554 : george 545 fun log2 n = (* n must be > 0!!! *)
555 :     let fun loop(0w1,pow) = pow
556 : george 761 | loop(w,pow) = loop(W32.>>(w, 0w1),pow+1)
557 : george 545 in loop(n,0) end
558 :     in if n > 1 andalso isPowerOf2 w then
559 : george 761 let val pow = T.LI(T.I.fromInt(32,log2 w))
560 : george 545 in if signed then
561 :     (* signed; simulate round towards zero *)
562 : george 909 let val label = Label.anon()
563 : george 545 val reg1 = expr e1
564 :     val opnd1 = I.Direct reg1
565 :     in if setZeroBit e1 then ()
566 :     else emit(I.CMPL{lsrc=opnd1, rsrc=I.Immed 0});
567 :     emit(I.JCC{cond=I.GE, opnd=immedLabel label});
568 :     emit(if n = 2 then
569 :     I.UNARY{unOp=I.INCL, opnd=opnd1}
570 :     else
571 :     I.BINARY{binOp=I.ADDL,
572 : george 761 src=I.Immed(n - 1),
573 : george 545 dst=opnd1});
574 :     defineLabel label;
575 :     shift(I.SARL, T.REG(32, reg1), pow)
576 :     end
577 :     else (* unsigned *)
578 :     shift(I.SHRL, e1, pow)
579 :     end
580 :     else
581 :     (* note the only way we can overflow is if
582 :     * n = 0 or n = -1
583 :     *)
584 :     divrem(signed, overflow andalso (n = ~1 orelse n = 0),
585 :     e1, e2, eax)
586 :     end
587 :     | divide(signed, overflow, e1, e2) =
588 :     divrem(signed, overflow, e1, e2, eax)
589 : monnier 247
590 : george 545 fun rem(signed, overflow, e1, e2) =
591 :     divrem(signed, overflow, e1, e2, edx)
592 : leunga 815
593 :     (* Makes sure the destination must be a register *)
594 :     fun dstMustBeReg f =
595 :     if isMemReg rd then
596 :     let val tmpR = newReg()
597 :     val tmp = I.Direct(tmpR)
598 :     in f(tmpR, tmp); move(tmp, rdOpnd) end
599 :     else f(rd, rdOpnd)
600 :    
601 : george 545 (* unsigned integer multiplication *)
602 :     fun uMultiply(e1, e2) =
603 :     (* note e2 can never be (I.Direct edx) *)
604 :     (move(operand e1, eax);
605 : leunga 815 mark(I.MULTDIV{multDivOp=I.MULL1,
606 : george 545 src=regOrMem(operand e2)},an);
607 :     move(eax, rdOpnd)
608 :     )
609 :    
610 :     (* signed integer multiplication:
611 :     * The only forms that are allowed that also sets the
612 :     * OF and CF flags are:
613 :     *
614 : leunga 815 * (dst) (src1) (src2)
615 : george 545 * imul r32, r32/m32, imm8
616 : leunga 815 * (dst) (src)
617 : george 545 * imul r32, imm8
618 :     * imul r32, imm32
619 : leunga 815 * imul r32, r32/m32
620 :     * Note: destination must be a register!
621 : george 545 *)
622 :     fun multiply(e1, e2) =
623 : leunga 815 dstMustBeReg(fn (rd, rdOpnd) =>
624 :     let fun doit(i1 as I.Immed _, i2 as I.Immed _) =
625 :     (move(i1, rdOpnd);
626 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=i2},an))
627 :     | doit(rm, i2 as I.Immed _) = doit(i2, rm)
628 :     | doit(imm as I.Immed(i), rm) =
629 :     mark(I.MUL3{dst=rd, src1=rm, src2=i},an)
630 :     | doit(r1 as I.Direct _, r2 as I.Direct _) =
631 :     (move(r1, rdOpnd);
632 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=r2},an))
633 :     | doit(r1 as I.Direct _, rm) =
634 :     (move(r1, rdOpnd);
635 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=rm},an))
636 :     | doit(rm, r as I.Direct _) = doit(r, rm)
637 :     | doit(rm1, rm2) =
638 : george 545 if equalRd rm2 then
639 :     let val tmpR = newReg()
640 :     val tmp = I.Direct tmpR
641 :     in move(rm1, tmp);
642 : leunga 815 mark(I.BINARY{binOp=I.IMULL, dst=tmp, src=rm2},an);
643 :     move(tmp, rdOpnd)
644 : george 545 end
645 :     else
646 : leunga 815 (move(rm1, rdOpnd);
647 :     mark(I.BINARY{binOp=I.IMULL, dst=rdOpnd, src=rm2},an)
648 : george 545 )
649 :     val (opnd1, opnd2) = (operand e1, operand e2)
650 : leunga 815 in doit(opnd1, opnd2)
651 : george 545 end
652 : leunga 815 )
653 : monnier 247
654 : george 545 (* Emit a load instruction; makes sure that the destination
655 :     * is a register
656 :     *)
657 :     fun genLoad(mvOp, ea, mem) =
658 :     dstMustBeReg(fn (_, dst) =>
659 :     mark(I.MOVE{mvOp=mvOp, src=address(ea, mem), dst=dst},an))
660 :    
661 :     (* Generate a zero extended loads *)
662 :     fun load8(ea, mem) = genLoad(I.MOVZBL, ea, mem)
663 :     fun load16(ea, mem) = genLoad(I.MOVZWL, ea, mem)
664 :     fun load8s(ea, mem) = genLoad(I.MOVSBL, ea, mem)
665 :     fun load16s(ea, mem) = genLoad(I.MOVSWL, ea, mem)
666 :     fun load32(ea, mem) = genLoad(I.MOVL, ea, mem)
667 :    
668 :     (* Generate a sign extended loads *)
669 :    
670 :     (* Generate setcc instruction:
671 :     * semantics: MV(rd, COND(_, T.CMP(ty, cc, t1, t2), yes, no))
672 : leunga 583 * Bug, if eax is either t1 or t2 then problem will occur!!!
673 :     * Note that we have to use eax as the destination of the
674 :     * setcc because it only works on the registers
675 :     * %al, %bl, %cl, %dl and %[abcd]h. The last four registers
676 :     * are inaccessible in 32 bit mode.
677 : george 545 *)
678 :     fun setcc(ty, cc, t1, t2, yes, no) =
679 : leunga 583 let val (cc, yes, no) =
680 :     if yes > no then (cc, yes, no)
681 :     else (T.Basis.negateCond cc, no, yes)
682 : george 545 in (* Clear the destination first.
683 :     * This this because stupid SETcc
684 :     * only writes to the low order
685 :     * byte. That's Intel architecture, folks.
686 :     *)
687 : leunga 695 case (yes, no, cc) of
688 :     (1, 0, T.LT) =>
689 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
690 :     in move(tmp, rdOpnd);
691 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
692 :     end
693 :     | (1, 0, T.GT) =>
694 :     let val tmp = I.Direct(expr(T.SUB(32,t1,t2)))
695 :     in emit(I.UNARY{unOp=I.NOTL,opnd=tmp});
696 :     move(tmp, rdOpnd);
697 :     emit(I.BINARY{binOp=I.SHRL,src=I.Immed 31,dst=rdOpnd})
698 :     end
699 :     | (1, 0, _) => (* normal case *)
700 : george 545 let val cc = cmp(true, ty, cc, t1, t2, [])
701 : leunga 583 in mark(I.SET{cond=cond cc, opnd=eax}, an);
702 : leunga 695 emit(I.BINARY{binOp=I.ANDL,src=I.Immed 255, dst=eax});
703 : leunga 583 move(eax, rdOpnd)
704 :     end
705 : leunga 695 | (C1, C2, _) =>
706 : george 545 (* general case;
707 : leunga 583 * from the Intel optimization guide p3-5
708 :     *)
709 : leunga 695 let val _ = zero eax;
710 :     val cc = cmp(true, ty, cc, t1, t2, [])
711 : leunga 583 in case C1-C2 of
712 :     D as (1 | 2 | 3 | 4 | 5 | 8 | 9) =>
713 :     let val (base,scale) =
714 :     case D of
715 :     1 => (NONE, 0)
716 :     | 2 => (NONE, 1)
717 :     | 3 => (SOME C.eax, 1)
718 :     | 4 => (NONE, 2)
719 :     | 5 => (SOME C.eax, 2)
720 :     | 8 => (NONE, 3)
721 :     | 9 => (SOME C.eax, 3)
722 :     val addr = I.Indexed{base=base,
723 :     index=C.eax,
724 :     scale=scale,
725 :     disp=I.Immed C2,
726 : george 545 mem=readonly}
727 : leunga 583 val tmpR = newReg()
728 :     val tmp = I.Direct tmpR
729 :     in emit(I.SET{cond=cond cc, opnd=eax});
730 :     mark(I.LEA{r32=tmpR, addr=addr}, an);
731 :     move(tmp, rdOpnd)
732 :     end
733 :     | D =>
734 :     (emit(I.SET{cond=cond(T.Basis.negateCond cc),
735 :     opnd=eax});
736 :     emit(I.UNARY{unOp=I.DECL, opnd=eax});
737 :     emit(I.BINARY{binOp=I.ANDL,
738 :     src=I.Immed D, dst=eax});
739 :     if C2 = 0 then
740 :     move(eax, rdOpnd)
741 :     else
742 :     let val tmpR = newReg()
743 :     val tmp = I.Direct tmpR
744 :     in mark(I.LEA{addr=
745 :     I.Displace{
746 :     base=C.eax,
747 :     disp=I.Immed C2,
748 :     mem=readonly},
749 :     r32=tmpR}, an);
750 :     move(tmp, rdOpnd)
751 :     end
752 :     )
753 :     end
754 : george 545 end (* setcc *)
755 :    
756 :     (* Generate cmovcc instruction.
757 :     * on Pentium Pro and Pentium II only
758 :     *)
759 :     fun cmovcc(ty, cc, t1, t2, yes, no) =
760 :     let fun genCmov(dstR, _) =
761 :     let val _ = doExpr(no, dstR, []) (* false branch *)
762 :     val cc = cmp(true, ty, cc, t1, t2, []) (* compare *)
763 :     in mark(I.CMOV{cond=cond cc, src=operand yes, dst=dstR}, an)
764 :     end
765 :     in dstMustBeReg genCmov
766 :     end
767 :    
768 :     fun unknownExp exp = doExpr(Gen.compileRexp exp, rd, an)
769 : monnier 247
770 : leunga 606 (* Add n to rd *)
771 :     fun addN n =
772 :     let val n = operand n
773 :     val src = if isMemReg rd then immedOrReg n else n
774 :     in mark(I.BINARY{binOp=I.ADDL, src=src, dst=rdOpnd}, an) end
775 :    
776 : george 545 (* Generate addition *)
777 :     fun addition(e1, e2) =
778 : leunga 606 case e1 of
779 : george 889 T.REG(_,rs) => if CB.sameColor(rs,rd) then addN e2
780 : leunga 744 else addition1(e1,e2)
781 : leunga 606 | _ => addition1(e1,e2)
782 :     and addition1(e1, e2) =
783 :     case e2 of
784 : george 889 T.REG(_,rs) => if CB.sameColor(rs,rd) then addN e1
785 : leunga 744 else addition2(e1,e2)
786 : leunga 606 | _ => addition2(e1,e2)
787 :     and addition2(e1,e2) =
788 : george 545 (dstMustBeReg(fn (dstR, _) =>
789 :     mark(I.LEA{r32=dstR, addr=address(exp, readonly)}, an))
790 :     handle EA => binaryComm(I.ADDL, e1, e2))
791 : monnier 247
792 :    
793 : george 545 in case exp of
794 :     T.REG(_,rs) =>
795 :     if isMemReg rs andalso isMemReg rd then
796 :     let val tmp = I.Direct(newReg())
797 : leunga 731 in move'(I.MemReg rs, tmp, an);
798 : george 545 move'(tmp, rdOpnd, [])
799 :     end
800 :     else move'(IntReg rs, rdOpnd, an)
801 : george 761 | T.LI z => let
802 :     val n = toInt32 z
803 :     in
804 :     if n=0 then
805 :     (* As per Fermin's request, special optimization for rd := 0.
806 :     * Currently we don't bother with the size.
807 :     *)
808 :     if isMemReg rd then move'(I.Immed 0, rdOpnd, an)
809 :     else mark(I.BINARY{binOp=I.XORL, src=rdOpnd, dst=rdOpnd}, an)
810 :     else
811 :     move'(I.Immed(n), rdOpnd, an)
812 :     end
813 : leunga 775 | (T.CONST _ | T.LABEL _) =>
814 :     move'(I.ImmedLabel exp, rdOpnd, an)
815 :     | T.LABEXP le => move'(I.ImmedLabel le, rdOpnd, an)
816 : monnier 247
817 : george 545 (* 32-bit addition *)
818 : george 761 | T.ADD(32, e1, e2 as T.LI n) => let
819 :     val n = toInt32 n
820 :     in
821 :     case n
822 :     of 1 => unary(I.INCL, e1)
823 :     | ~1 => unary(I.DECL, e1)
824 :     | _ => addition(e1, e2)
825 :     end
826 :     | T.ADD(32, e1 as T.LI n, e2) => let
827 :     val n = toInt32 n
828 :     in
829 :     case n
830 :     of 1 => unary(I.INCL, e2)
831 :     | ~1 => unary(I.DECL, e2)
832 :     | _ => addition(e1, e2)
833 :     end
834 : george 545 | T.ADD(32, e1, e2) => addition(e1, e2)
835 : monnier 247
836 : leunga 695 (* 32-bit addition but set the flag!
837 :     * This is a stupid hack for now.
838 :     *)
839 : george 761 | T.ADD(0, e, e1 as T.LI n) => let
840 :     val n = T.I.toInt(32, n)
841 :     in
842 :     if n=1 then unary(I.INCL, e)
843 :     else if n = ~1 then unary(I.DECL, e)
844 :     else binaryComm(I.ADDL, e, e1)
845 :     end
846 :     | T.ADD(0, e1 as T.LI n, e) => let
847 :     val n = T.I.toInt(32, n)
848 :     in
849 :     if n=1 then unary(I.INCL, e)
850 :     else if n = ~1 then unary(I.DECL, e)
851 :     else binaryComm(I.ADDL, e1, e)
852 :     end
853 :     | T.ADD(0, e1, e2) => binaryComm(I.ADDL, e1, e2)
854 :    
855 : george 545 (* 32-bit subtraction *)
856 : george 761 | T.SUB(32, e1, e2 as T.LI n) => let
857 :     val n = toInt32 n
858 :     in
859 :     case n
860 :     of 0 => doExpr(e1, rd, an)
861 :     | 1 => unary(I.DECL, e1)
862 :     | ~1 => unary(I.INCL, e1)
863 :     | _ => binary(I.SUBL, e1, e2)
864 :     end
865 :     | T.SUB(32, e1 as T.LI n, e2) =>
866 :     if T.I.isZero n then unary(I.NEGL, e2)
867 :     else binary(I.SUBL, e1, e2)
868 : george 545 | T.SUB(32, e1, e2) => binary(I.SUBL, e1, e2)
869 : monnier 247
870 : george 545 | T.MULU(32, x, y) => uMultiply(x, y)
871 :     | T.DIVU(32, x, y) => divide(false, false, x, y)
872 :     | T.REMU(32, x, y) => rem(false, false, x, y)
873 : monnier 247
874 : george 545 | T.MULS(32, x, y) => multiply(x, y)
875 :     | T.DIVS(32, x, y) => divide(true, false, x, y)
876 :     | T.REMS(32, x, y) => rem(true, false, x, y)
877 : monnier 247
878 : george 545 | T.ADDT(32, x, y) => (binaryComm(I.ADDL, x, y); trap())
879 :     | T.SUBT(32, x, y) => (binary(I.SUBL, x, y); trap())
880 :     | T.MULT(32, x, y) => (multiply(x, y); trap())
881 :     | T.DIVT(32, x, y) => divide(true, true, x, y)
882 :     | T.REMT(32, x, y) => rem(true, true, x, y)
883 : monnier 247
884 : george 545 | T.ANDB(32, x, y) => binaryComm(I.ANDL, x, y)
885 :     | T.ORB(32, x, y) => binaryComm(I.ORL, x, y)
886 :     | T.XORB(32, x, y) => binaryComm(I.XORL, x, y)
887 :     | T.NOTB(32, x) => unary(I.NOTL, x)
888 : monnier 247
889 : george 545 | T.SRA(32, x, y) => shift(I.SARL, x, y)
890 :     | T.SRL(32, x, y) => shift(I.SHRL, x, y)
891 :     | T.SLL(32, x, y) => shift(I.SHLL, x, y)
892 : monnier 247
893 : george 545 | T.LOAD(8, ea, mem) => load8(ea, mem)
894 :     | T.LOAD(16, ea, mem) => load16(ea, mem)
895 :     | T.LOAD(32, ea, mem) => load32(ea, mem)
896 : monnier 498
897 : leunga 776 | T.SX(32,8,T.LOAD(8,ea,mem)) => load8s(ea, mem)
898 :     | T.SX(32,16,T.LOAD(16,ea,mem)) => load16s(ea, mem)
899 :     | T.ZX(32,8,T.LOAD(8,ea,mem)) => load8(ea, mem)
900 : leunga 779 | T.ZX(32,16,T.LOAD(16,ea,mem)) => load16(ea, mem)
901 : leunga 776
902 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), T.LI yes, T.LI no) =>
903 : leunga 583 setcc(ty, cc, t1, t2, toInt32 yes, toInt32 no)
904 : george 545 | T.COND(32, T.CMP(ty, cc, t1, t2), yes, no) =>
905 :     (case !arch of (* PentiumPro and higher has CMOVcc *)
906 :     Pentium => unknownExp exp
907 :     | _ => cmovcc(ty, cc, t1, t2, yes, no)
908 :     )
909 :     | T.LET(s,e) => (doStmt s; doExpr(e, rd, an))
910 :     | T.MARK(e, A.MARKREG f) => (f rd; doExpr(e, rd, an))
911 :     | T.MARK(e, a) => doExpr(e, rd, a::an)
912 :     | T.PRED(e,c) => doExpr(e, rd, A.CTRLUSE c::an)
913 : george 555 | T.REXT e =>
914 :     ExtensionComp.compileRext (reducer()) {e=e, rd=rd, an=an}
915 : george 545 (* simplify and try again *)
916 :     | exp => unknownExp exp
917 :     end (* doExpr *)
918 : monnier 247
919 : george 545 (* generate an expression and return its result register
920 :     * If rewritePseudo is on, the result is guaranteed to be in a
921 :     * non memReg register
922 :     *)
923 :     and expr(exp as T.REG(_, rd)) =
924 :     if isMemReg rd then genExpr exp else rd
925 :     | expr exp = genExpr exp
926 : monnier 247
927 : george 545 and genExpr exp =
928 :     let val rd = newReg() in doExpr(exp, rd, []); rd end
929 : monnier 247
930 : george 545 (* Compare an expression with zero.
931 :     * On the x86, TEST is superior to AND for doing the same thing,
932 :     * since it doesn't need to write out the result in a register.
933 :     *)
934 : leunga 695 and cmpWithZero(cc as (T.EQ | T.NE), e as T.ANDB(ty, a, b), an) =
935 : george 545 (case ty of
936 : leunga 695 8 => test(I.TESTB, a, b, an)
937 :     | 16 => test(I.TESTW, a, b, an)
938 :     | 32 => test(I.TESTL, a, b, an)
939 :     | _ => doExpr(e, newReg(), an);
940 :     cc)
941 :     | cmpWithZero(cc, e, an) =
942 :     let val e =
943 :     case e of (* hack to disable the lea optimization XXX *)
944 :     T.ADD(_, a, b) => T.ADD(0, a, b)
945 :     | e => e
946 :     in doExpr(e, newReg(), an); cc end
947 : monnier 247
948 : george 545 (* Emit a test.
949 :     * The available modes are
950 :     * r/m, r
951 :     * r/m, imm
952 :     * On selecting the right instruction: TESTL/TESTW/TESTB.
953 :     * When anding an operand with a constant
954 :     * that fits within 8 (or 16) bits, it is possible to use TESTB,
955 :     * (or TESTW) instead of TESTL. Because x86 is little endian,
956 :     * this works for memory operands too. However, with TESTB, it is
957 :     * not possible to use registers other than
958 :     * AL, CL, BL, DL, and AH, CH, BH, DH. So, the best way is to
959 :     * perform register allocation first, and if the operand registers
960 :     * are one of EAX, ECX, EBX, or EDX, replace the TESTL instruction
961 :     * by TESTB.
962 :     *)
963 : leunga 695 and test(testopcode, a, b, an) =
964 : george 545 let val (_, opnd1, opnd2) = commuteComparison(T.EQ, true, a, b)
965 :     (* translate r, r/m => r/m, r *)
966 :     val (opnd1, opnd2) =
967 :     if isMemOpnd opnd2 then (opnd2, opnd1) else (opnd1, opnd2)
968 : leunga 695 in mark(testopcode{lsrc=opnd1, rsrc=opnd2}, an)
969 : george 545 end
970 : monnier 247
971 : leunga 815 (* %eflags <- src *)
972 :     and moveToEflags src =
973 : george 889 if CB.sameColor(src, C.eflags) then ()
974 : leunga 815 else (move(I.Direct src, eax); emit(I.LAHF))
975 :    
976 :     (* dst <- %eflags *)
977 :     and moveFromEflags dst =
978 : george 889 if CB.sameColor(dst, C.eflags) then ()
979 : leunga 815 else (emit(I.SAHF); move(eax, I.Direct dst))
980 :    
981 : george 545 (* generate a condition code expression
982 : leunga 744 * The zero is for setting the condition code!
983 :     * I have no idea why this is used.
984 :     *)
985 :     and doCCexpr(T.CMP(ty, cc, t1, t2), rd, an) =
986 : leunga 815 (cmp(false, ty, cc, t1, t2, an);
987 :     moveFromEflags rd
988 :     )
989 :     | doCCexpr(T.CC(cond,rs), rd, an) =
990 : george 889 if CB.sameColor(rs,C.eflags) orelse CB.sameColor(rd,C.eflags) then
991 : leunga 815 (moveToEflags rs; moveFromEflags rd)
992 : leunga 744 else
993 : leunga 815 move'(I.Direct rs, I.Direct rd, an)
994 : george 545 | doCCexpr(T.CCMARK(e,A.MARKREG f),rd,an) = (f rd; doCCexpr(e,rd,an))
995 :     | doCCexpr(T.CCMARK(e,a), rd, an) = doCCexpr(e,rd,a::an)
996 :     | doCCexpr(T.CCEXT e, cd, an) =
997 : george 555 ExtensionComp.compileCCext (reducer()) {e=e, ccd=cd, an=an}
998 : george 545 | doCCexpr _ = error "doCCexpr"
999 : monnier 247
1000 : george 545 and ccExpr e = error "ccExpr"
1001 : monnier 247
1002 : george 545 (* generate a comparison and sets the condition code;
1003 :     * return the actual cc used. If the flag swapable is true,
1004 :     * we can also reorder the operands.
1005 :     *)
1006 :     and cmp(swapable, ty, cc, t1, t2, an) =
1007 : leunga 695 (* == and <> can be always be reordered *)
1008 :     let val swapable = swapable orelse cc = T.EQ orelse cc = T.NE
1009 :     in (* Sometimes the comparison is not necessary because
1010 :     * the bits are already set!
1011 :     *)
1012 :     if isZero t1 andalso setZeroBit2 t2 then
1013 :     if swapable then
1014 :     cmpWithZero(T.Basis.swapCond cc, t2, an)
1015 :     else (* can't reorder the comparison! *)
1016 :     genCmp(ty, false, cc, t1, t2, an)
1017 :     else if isZero t2 andalso setZeroBit2 t1 then
1018 :     cmpWithZero(cc, t1, an)
1019 :     else genCmp(ty, swapable, cc, t1, t2, an)
1020 :     end
1021 : monnier 247
1022 : george 545 (* Give a and b which are the operands to a comparison (or test)
1023 :     * Return the appropriate condition code and operands.
1024 :     * The available modes are:
1025 :     * r/m, imm
1026 :     * r/m, r
1027 :     * r, r/m
1028 :     *)
1029 :     and commuteComparison(cc, swapable, a, b) =
1030 :     let val (opnd1, opnd2) = (operand a, operand b)
1031 :     in (* Try to fold in the operands whenever possible *)
1032 :     case (isImmediate opnd1, isImmediate opnd2) of
1033 :     (true, true) => (cc, moveToReg opnd1, opnd2)
1034 :     | (true, false) =>
1035 :     if swapable then (T.Basis.swapCond cc, opnd2, opnd1)
1036 :     else (cc, moveToReg opnd1, opnd2)
1037 :     | (false, true) => (cc, opnd1, opnd2)
1038 :     | (false, false) =>
1039 :     (case (opnd1, opnd2) of
1040 :     (_, I.Direct _) => (cc, opnd1, opnd2)
1041 :     | (I.Direct _, _) => (cc, opnd1, opnd2)
1042 :     | (_, _) => (cc, moveToReg opnd1, opnd2)
1043 :     )
1044 :     end
1045 :    
1046 :     (* generate a real comparison; return the real cc used *)
1047 :     and genCmp(ty, swapable, cc, a, b, an) =
1048 :     let val (cc, opnd1, opnd2) = commuteComparison(cc, swapable, a, b)
1049 :     in mark(I.CMPL{lsrc=opnd1, rsrc=opnd2}, an); cc
1050 :     end
1051 : monnier 247
1052 : george 545 (* generate code for jumps *)
1053 : leunga 775 and jmp(lexp as T.LABEL lab, labs, an) =
1054 : george 545 mark(I.JMP(I.ImmedLabel lexp, [lab]), an)
1055 : leunga 775 | jmp(T.LABEXP le, labs, an) = mark(I.JMP(I.ImmedLabel le, labs), an)
1056 :     | jmp(ea, labs, an) = mark(I.JMP(operand ea, labs), an)
1057 : george 545
1058 :     (* convert mlrisc to cellset:
1059 :     *)
1060 :     and cellset mlrisc =
1061 : jhr 900 let val addCCReg = CB.CellSet.add
1062 : george 545 fun g([],acc) = acc
1063 :     | g(T.GPR(T.REG(_,r))::regs,acc) = g(regs,C.addReg(r,acc))
1064 :     | g(T.FPR(T.FREG(_,f))::regs,acc) = g(regs,C.addFreg(f,acc))
1065 :     | g(T.CCR(T.CC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1066 :     | g(T.CCR(T.FCC(_,cc))::regs,acc) = g(regs,addCCReg(cc,acc))
1067 :     | g(_::regs, acc) = g(regs, acc)
1068 :     in g(mlrisc, C.empty) end
1069 :    
1070 :     (* generate code for calls *)
1071 : blume 839 and call(ea, flow, def, use, mem, cutsTo, an, pops) =
1072 : leunga 815 let fun return(set, []) = set
1073 :     | return(set, a::an) =
1074 :     case #peek A.RETURN_ARG a of
1075 : jhr 900 SOME r => return(CB.CellSet.add(r, set), an)
1076 : leunga 815 | NONE => return(set, an)
1077 : blume 839 in
1078 :     mark(I.CALL{opnd=operand ea,defs=cellset(def),uses=cellset(use),
1079 :     return=return(C.empty,an),cutsTo=cutsTo,mem=mem,
1080 :     pops=pops},an)
1081 : leunga 815 end
1082 : george 545
1083 : leunga 815 (* generate code for integer stores; first move data to %eax
1084 :     * This is mainly because we can't allocate to registers like
1085 :     * ah, dl, dx etc.
1086 :     *)
1087 :     and genStore(mvOp, ea, d, mem, an) =
1088 :     let val src =
1089 : george 545 case immedOrReg(operand d) of
1090 :     src as I.Direct r =>
1091 : george 889 if CB.sameColor(r,C.eax)
1092 : leunga 744 then src else (move(src, eax); eax)
1093 : george 545 | src => src
1094 : leunga 815 in mark(I.MOVE{mvOp=mvOp, src=src, dst=address(ea,mem)},an)
1095 : george 545 end
1096 : leunga 815
1097 :     (* generate code for 8-bit integer stores *)
1098 :     (* movb has to use %eax as source. Stupid x86! *)
1099 :     and store8(ea, d, mem, an) = genStore(I.MOVB, ea, d, mem, an)
1100 : blume 818 and store16(ea, d, mem, an) =
1101 :     mark(I.MOVE{mvOp=I.MOVW, src=immedOrReg(operand d), dst=address(ea, mem)}, an)
1102 : george 545 and store32(ea, d, mem, an) =
1103 :     move'(immedOrReg(operand d), address(ea, mem), an)
1104 :    
1105 :     (* generate code for branching *)
1106 :     and branch(T.CMP(ty, cc, t1, t2), lab, an) =
1107 :     (* allow reordering of operands *)
1108 :     let val cc = cmp(true, ty, cc, t1, t2, [])
1109 :     in mark(I.JCC{cond=cond cc, opnd=immedLabel lab}, an) end
1110 :     | branch(T.FCMP(fty, fcc, t1, t2), lab, an) =
1111 :     fbranch(fty, fcc, t1, t2, lab, an)
1112 :     | branch(ccexp, lab, an) =
1113 : leunga 744 (doCCexpr(ccexp, C.eflags, []);
1114 : george 545 mark(I.JCC{cond=cond(Gen.condOf ccexp), opnd=immedLabel lab}, an)
1115 :     )
1116 :    
1117 :     (* generate code for floating point compare and branch *)
1118 :     and fbranch(fty, fcc, t1, t2, lab, an) =
1119 : leunga 731 let fun ignoreOrder (T.FREG _) = true
1120 :     | ignoreOrder (T.FLOAD _) = true
1121 :     | ignoreOrder (T.FMARK(e,_)) = ignoreOrder e
1122 :     | ignoreOrder _ = false
1123 :    
1124 :     fun compare'() = (* Sethi-Ullman style *)
1125 :     (if ignoreOrder t1 orelse ignoreOrder t2 then
1126 :     (reduceFexp(fty, t2, []); reduceFexp(fty, t1, []))
1127 :     else (reduceFexp(fty, t1, []); reduceFexp(fty, t2, []);
1128 :     emit(I.FXCH{opnd=C.ST(1)}));
1129 :     emit(I.FUCOMPP);
1130 :     fcc
1131 :     )
1132 :    
1133 :     fun compare''() =
1134 :     (* direct style *)
1135 :     (* Try to make lsrc the memory operand *)
1136 :     let val lsrc = foperand(fty, t1)
1137 :     val rsrc = foperand(fty, t2)
1138 :     val fsize = fsize fty
1139 :     fun cmp(lsrc, rsrc, fcc) =
1140 :     (emit(I.FCMP{fsize=fsize,lsrc=lsrc,rsrc=rsrc}); fcc)
1141 :     in case (lsrc, rsrc) of
1142 :     (I.FPR _, I.FPR _) => cmp(lsrc, rsrc, fcc)
1143 :     | (I.FPR _, mem) => cmp(mem,lsrc,T.Basis.swapFcond fcc)
1144 :     | (mem, I.FPR _) => cmp(lsrc, rsrc, fcc)
1145 :     | (lsrc, rsrc) => (* can't be both memory! *)
1146 :     let val ftmpR = newFreg()
1147 :     val ftmp = I.FPR ftmpR
1148 :     in emit(I.FMOVE{fsize=fsize,src=rsrc,dst=ftmp});
1149 :     cmp(lsrc, ftmp, fcc)
1150 :     end
1151 :     end
1152 :    
1153 :     fun compare() =
1154 :     if enableFastFPMode andalso !fast_floating_point
1155 :     then compare''() else compare'()
1156 :    
1157 : george 545 fun andil i = emit(I.BINARY{binOp=I.ANDL,src=I.Immed(i),dst=eax})
1158 : leunga 585 fun testil i = emit(I.TESTL{lsrc=eax,rsrc=I.Immed(i)})
1159 : george 545 fun xoril i = emit(I.BINARY{binOp=I.XORL,src=I.Immed(i),dst=eax})
1160 :     fun cmpil i = emit(I.CMPL{rsrc=I.Immed(i), lsrc=eax})
1161 :     fun j(cc, lab) = mark(I.JCC{cond=cc, opnd=immedLabel lab},an)
1162 :     fun sahf() = emit(I.SAHF)
1163 : leunga 731 fun branch(fcc) =
1164 : george 545 case fcc
1165 :     of T.== => (andil 0x4400; xoril 0x4000; j(I.EQ, lab))
1166 :     | T.?<> => (andil 0x4400; xoril 0x4000; j(I.NE, lab))
1167 :     | T.? => (sahf(); j(I.P,lab))
1168 :     | T.<=> => (sahf(); j(I.NP,lab))
1169 : leunga 585 | T.> => (testil 0x4500; j(I.EQ,lab))
1170 :     | T.?<= => (testil 0x4500; j(I.NE,lab))
1171 :     | T.>= => (testil 0x500; j(I.EQ,lab))
1172 :     | T.?< => (testil 0x500; j(I.NE,lab))
1173 : george 545 | T.< => (andil 0x4500; cmpil 0x100; j(I.EQ,lab))
1174 :     | T.?>= => (andil 0x4500; cmpil 0x100; j(I.NE,lab))
1175 :     | T.<= => (andil 0x4100; cmpil 0x100; j(I.EQ,lab);
1176 :     cmpil 0x4000; j(I.EQ,lab))
1177 : leunga 585 | T.?> => (sahf(); j(I.P,lab); testil 0x4100; j(I.EQ,lab))
1178 :     | T.<> => (testil 0x4400; j(I.EQ,lab))
1179 :     | T.?= => (testil 0x4400; j(I.NE,lab))
1180 : george 545 | _ => error "fbranch"
1181 :     (*esac*)
1182 : leunga 731 val fcc = compare()
1183 :     in emit I.FNSTSW;
1184 :     branch(fcc)
1185 : monnier 411 end
1186 : monnier 247
1187 : leunga 731 (*========================================================
1188 :     * Floating point code generation starts here.
1189 :     * Some generic fp routines first.
1190 :     *========================================================*)
1191 :    
1192 :     (* Can this tree be folded into the src operand of a floating point
1193 :     * operations?
1194 :     *)
1195 :     and foldableFexp(T.FREG _) = true
1196 :     | foldableFexp(T.FLOAD _) = true
1197 :     | foldableFexp(T.CVTI2F(_, (16 | 32), _)) = true
1198 :     | foldableFexp(T.CVTF2F(_, _, t)) = foldableFexp t
1199 :     | foldableFexp(T.FMARK(t, _)) = foldableFexp t
1200 :     | foldableFexp _ = false
1201 :    
1202 :     (* Move integer e of size ty into a memory location.
1203 :     * Returns a quadruple:
1204 :     * (INTEGER,return ty,effect address of memory location,cleanup code)
1205 :     *)
1206 :     and convertIntToFloat(ty, e) =
1207 :     let val opnd = operand e
1208 :     in if isMemOpnd opnd andalso (ty = 16 orelse ty = 32)
1209 :     then (INTEGER, ty, opnd, [])
1210 :     else
1211 : leunga 815 let val {instrs, tempMem, cleanup} =
1212 :     cvti2f{ty=ty, src=opnd, an=getAnnotations()}
1213 : leunga 731 in emits instrs;
1214 :     (INTEGER, 32, tempMem, cleanup)
1215 :     end
1216 :     end
1217 :    
1218 :     (*========================================================
1219 :     * Sethi-Ullman based floating point code generation as
1220 :     * implemented by Lal
1221 :     *========================================================*)
1222 :    
1223 : george 545 and fld(32, opnd) = I.FLDS opnd
1224 :     | fld(64, opnd) = I.FLDL opnd
1225 : george 555 | fld(80, opnd) = I.FLDT opnd
1226 : george 545 | fld _ = error "fld"
1227 :    
1228 : leunga 565 and fild(16, opnd) = I.FILD opnd
1229 :     | fild(32, opnd) = I.FILDL opnd
1230 :     | fild(64, opnd) = I.FILDLL opnd
1231 :     | fild _ = error "fild"
1232 :    
1233 :     and fxld(INTEGER, ty, opnd) = fild(ty, opnd)
1234 :     | fxld(REAL, fty, opnd) = fld(fty, opnd)
1235 :    
1236 : george 545 and fstp(32, opnd) = I.FSTPS opnd
1237 :     | fstp(64, opnd) = I.FSTPL opnd
1238 : george 555 | fstp(80, opnd) = I.FSTPT opnd
1239 : george 545 | fstp _ = error "fstp"
1240 :    
1241 :     (* generate code for floating point stores *)
1242 : leunga 731 and fstore'(fty, ea, d, mem, an) =
1243 : george 545 (case d of
1244 :     T.FREG(fty, fs) => emit(fld(fty, I.FDirect fs))
1245 :     | _ => reduceFexp(fty, d, []);
1246 :     mark(fstp(fty, address(ea, mem)), an)
1247 :     )
1248 :    
1249 : leunga 731 (* generate code for floating point loads *)
1250 :     and fload'(fty, ea, mem, fd, an) =
1251 :     let val ea = address(ea, mem)
1252 :     in mark(fld(fty, ea), an);
1253 : george 889 if CB.sameColor(fd,ST0) then ()
1254 : leunga 744 else emit(fstp(fty, I.FDirect fd))
1255 : leunga 731 end
1256 :    
1257 :     and fexpr' e = (reduceFexp(64, e, []); C.ST(0))
1258 : george 545
1259 :     (* generate floating point expression and put the result in fd *)
1260 : leunga 731 and doFexpr'(fty, T.FREG(_, fs), fd, an) =
1261 : george 889 (if CB.sameColor(fs,fd) then ()
1262 : george 1009 else mark'(I.COPY{k=CB.FP, sz=64, dst=[fd], src=[fs], tmp=NONE}, an)
1263 : george 545 )
1264 : leunga 731 | doFexpr'(_, T.FLOAD(fty, ea, mem), fd, an) =
1265 :     fload'(fty, ea, mem, fd, an)
1266 :     | doFexpr'(fty, T.FEXT fexp, fd, an) =
1267 :     (ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an};
1268 : george 889 if CB.sameColor(fd,ST0) then () else emit(fstp(fty, I.FDirect fd))
1269 : leunga 731 )
1270 :     | doFexpr'(fty, e, fd, an) =
1271 : george 545 (reduceFexp(fty, e, []);
1272 : george 889 if CB.sameColor(fd,ST0) then ()
1273 : leunga 744 else mark(fstp(fty, I.FDirect fd), an)
1274 : george 545 )
1275 :    
1276 :     (*
1277 :     * Generate floating point expression using Sethi-Ullman's scheme:
1278 :     * This function evaluates a floating point expression,
1279 :     * and put result in %ST(0).
1280 :     *)
1281 :     and reduceFexp(fty, fexp, an) =
1282 : george 555 let val ST = I.ST(C.ST 0)
1283 :     val ST1 = I.ST(C.ST 1)
1284 : leunga 593 val cleanupCode = ref [] : I.instruction list ref
1285 : george 545
1286 : leunga 565 datatype su_tree =
1287 :     LEAF of int * T.fexp * ans
1288 :     | BINARY of int * T.fty * fbinop * su_tree * su_tree * ans
1289 :     | UNARY of int * T.fty * I.funOp * su_tree * ans
1290 :     and fbinop = FADD | FSUB | FMUL | FDIV
1291 :     | FIADD | FISUB | FIMUL | FIDIV
1292 :     withtype ans = Annotations.annotations
1293 : monnier 247
1294 : leunga 565 fun label(LEAF(n, _, _)) = n
1295 :     | label(BINARY(n, _, _, _, _, _)) = n
1296 :     | label(UNARY(n, _, _, _, _)) = n
1297 : george 545
1298 : leunga 565 fun annotate(LEAF(n, x, an), a) = LEAF(n,x,a::an)
1299 :     | annotate(BINARY(n,t,b,x,y,an), a) = BINARY(n,t,b,x,y,a::an)
1300 :     | annotate(UNARY(n,t,u,x,an), a) = UNARY(n,t,u,x,a::an)
1301 : george 545
1302 : leunga 565 (* Generate expression tree with sethi-ullman numbers *)
1303 :     fun su(e as T.FREG _) = LEAF(1, e, [])
1304 :     | su(e as T.FLOAD _) = LEAF(1, e, [])
1305 :     | su(e as T.CVTI2F _) = LEAF(1, e, [])
1306 :     | su(T.CVTF2F(_, _, t)) = su t
1307 :     | su(T.FMARK(t, a)) = annotate(su t, a)
1308 :     | su(T.FABS(fty, t)) = suUnary(fty, I.FABS, t)
1309 :     | su(T.FNEG(fty, t)) = suUnary(fty, I.FCHS, t)
1310 :     | su(T.FSQRT(fty, t)) = suUnary(fty, I.FSQRT, t)
1311 :     | su(T.FADD(fty, t1, t2)) = suComBinary(fty,FADD,FIADD,t1,t2)
1312 :     | su(T.FMUL(fty, t1, t2)) = suComBinary(fty,FMUL,FIMUL,t1,t2)
1313 :     | su(T.FSUB(fty, t1, t2)) = suBinary(fty,FSUB,FISUB,t1,t2)
1314 :     | su(T.FDIV(fty, t1, t2)) = suBinary(fty,FDIV,FIDIV,t1,t2)
1315 :     | su _ = error "su"
1316 :    
1317 :     (* Try to fold the the memory operand or integer conversion *)
1318 :     and suFold(e as T.FREG _) = (LEAF(0, e, []), false)
1319 :     | suFold(e as T.FLOAD _) = (LEAF(0, e, []), false)
1320 :     | suFold(e as T.CVTI2F(_,(16 | 32),_)) = (LEAF(0, e, []), true)
1321 :     | suFold(T.CVTF2F(_, _, t)) = suFold t
1322 :     | suFold(T.FMARK(t, a)) =
1323 :     let val (t, integer) = suFold t
1324 :     in (annotate(t, a), integer) end
1325 :     | suFold e = (su e, false)
1326 :    
1327 :     (* Form unary tree *)
1328 :     and suUnary(fty, funary, t) =
1329 :     let val t = su t
1330 :     in UNARY(label t, fty, funary, t, [])
1331 : george 545 end
1332 : leunga 565
1333 :     (* Form binary tree *)
1334 :     and suBinary(fty, binop, ibinop, t1, t2) =
1335 :     let val t1 = su t1
1336 :     val (t2, integer) = suFold t2
1337 :     val n1 = label t1
1338 :     val n2 = label t2
1339 :     val n = if n1=n2 then n1+1 else Int.max(n1,n2)
1340 :     val myOp = if integer then ibinop else binop
1341 :     in BINARY(n, fty, myOp, t1, t2, [])
1342 : george 545 end
1343 : george 555
1344 : leunga 565 (* Try to fold in the operand if possible.
1345 :     * This only applies to commutative operations.
1346 :     *)
1347 :     and suComBinary(fty, binop, ibinop, t1, t2) =
1348 : leunga 731 let val (t1, t2) = if foldableFexp t2
1349 :     then (t1, t2) else (t2, t1)
1350 : leunga 565 in suBinary(fty, binop, ibinop, t1, t2) end
1351 :    
1352 :     and sameTree(LEAF(_, T.FREG(t1,f1), []),
1353 : leunga 744 LEAF(_, T.FREG(t2,f2), [])) =
1354 : george 889 t1 = t2 andalso CB.sameColor(f1,f2)
1355 : leunga 565 | sameTree _ = false
1356 :    
1357 :     (* Traverse tree and generate code *)
1358 :     fun gencode(LEAF(_, t, an)) = mark(fxld(leafEA t), an)
1359 :     | gencode(BINARY(_, _, binop, x, t2 as LEAF(0, y, a1), a2)) =
1360 :     let val _ = gencode x
1361 :     val (_, fty, src) = leafEA y
1362 :     fun gen(code) = mark(code, a1 @ a2)
1363 :     fun binary(oper32, oper64) =
1364 :     if sameTree(x, t2) then
1365 :     gen(I.FBINARY{binOp=oper64, src=ST, dst=ST})
1366 : george 555 else
1367 :     let val oper =
1368 : leunga 565 if isMemOpnd src then
1369 :     case fty of
1370 :     32 => oper32
1371 :     | 64 => oper64
1372 :     | _ => error "gencode: BINARY"
1373 :     else oper64
1374 :     in gen(I.FBINARY{binOp=oper, src=src, dst=ST}) end
1375 :     fun ibinary(oper16, oper32) =
1376 :     let val oper = case fty of
1377 :     16 => oper16
1378 :     | 32 => oper32
1379 :     | _ => error "gencode: IBINARY"
1380 :     in gen(I.FIBINARY{binOp=oper, src=src}) end
1381 :     in case binop of
1382 :     FADD => binary(I.FADDS, I.FADDL)
1383 :     | FSUB => binary(I.FDIVS, I.FSUBL)
1384 :     | FMUL => binary(I.FMULS, I.FMULL)
1385 :     | FDIV => binary(I.FDIVS, I.FDIVL)
1386 :     | FIADD => ibinary(I.FIADDS, I.FIADDL)
1387 :     | FISUB => ibinary(I.FIDIVS, I.FISUBL)
1388 :     | FIMUL => ibinary(I.FIMULS, I.FIMULL)
1389 :     | FIDIV => ibinary(I.FIDIVS, I.FIDIVL)
1390 :     end
1391 :     | gencode(BINARY(_, fty, binop, t1, t2, an)) =
1392 :     let fun doit(t1, t2, oper, operP, operRP) =
1393 :     let (* oper[P] => ST(1) := ST oper ST(1); [pop]
1394 :     * operR[P] => ST(1) := ST(1) oper ST; [pop]
1395 :     *)
1396 :     val n1 = label t1
1397 :     val n2 = label t2
1398 :     in if n1 < n2 andalso n1 <= 7 then
1399 :     (gencode t2;
1400 :     gencode t1;
1401 :     mark(I.FBINARY{binOp=operP, src=ST, dst=ST1}, an))
1402 :     else if n2 <= n1 andalso n2 <= 7 then
1403 :     (gencode t1;
1404 :     gencode t2;
1405 :     mark(I.FBINARY{binOp=operRP, src=ST, dst=ST1}, an))
1406 :     else
1407 :     let (* both labels > 7 *)
1408 :     val fs = I.FDirect(newFreg())
1409 :     in gencode t2;
1410 :     emit(fstp(fty, fs));
1411 :     gencode t1;
1412 :     mark(I.FBINARY{binOp=oper, src=fs, dst=ST}, an)
1413 :     end
1414 :     end
1415 :     in case binop of
1416 :     FADD => doit(t1,t2,I.FADDL,I.FADDP,I.FADDP)
1417 :     | FMUL => doit(t1,t2,I.FMULL,I.FMULP,I.FMULP)
1418 :     | FSUB => doit(t1,t2,I.FSUBL,I.FSUBP,I.FSUBRP)
1419 :     | FDIV => doit(t1,t2,I.FDIVL,I.FDIVP,I.FDIVRP)
1420 : george 545 | _ => error "gencode.BINARY"
1421 :     end
1422 : leunga 565 | gencode(UNARY(_, _, unaryOp, su, an)) =
1423 :     (gencode(su); mark(I.FUNARY(unaryOp),an))
1424 :    
1425 :     (* Generate code for a leaf.
1426 :     * Returns the type and an effective address
1427 :     *)
1428 :     and leafEA(T.FREG(fty, f)) = (REAL, fty, I.FDirect f)
1429 :     | leafEA(T.FLOAD(fty, ea, mem)) = (REAL, fty, address(ea, mem))
1430 : leunga 593 | leafEA(T.CVTI2F(_, 32, t)) = int2real(32, t)
1431 :     | leafEA(T.CVTI2F(_, 16, t)) = int2real(16, t)
1432 :     | leafEA(T.CVTI2F(_, 8, t)) = int2real(8, t)
1433 : leunga 565 | leafEA _ = error "leafEA"
1434 :    
1435 : leunga 731 and int2real(ty, e) =
1436 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1437 :     in cleanupCode := !cleanupCode @ cleanup;
1438 :     (INTEGER, ty, ea)
1439 : george 545 end
1440 : leunga 731
1441 :     in gencode(su fexp);
1442 :     emits(!cleanupCode)
1443 : george 545 end (*reduceFexp*)
1444 : leunga 731
1445 :     (*========================================================
1446 :     * This section generates 3-address style floating
1447 :     * point code.
1448 :     *========================================================*)
1449 :    
1450 :     and isize 16 = I.I16
1451 :     | isize 32 = I.I32
1452 :     | isize _ = error "isize"
1453 :    
1454 :     and fstore''(fty, ea, d, mem, an) =
1455 :     (floatingPointUsed := true;
1456 :     mark(I.FMOVE{fsize=fsize fty, dst=address(ea,mem),
1457 :     src=foperand(fty, d)},
1458 :     an)
1459 :     )
1460 :    
1461 :     and fload''(fty, ea, mem, d, an) =
1462 :     (floatingPointUsed := true;
1463 :     mark(I.FMOVE{fsize=fsize fty, src=address(ea,mem),
1464 :     dst=RealReg d}, an)
1465 :     )
1466 :    
1467 :     and fiload''(ity, ea, d, an) =
1468 :     (floatingPointUsed := true;
1469 :     mark(I.FILOAD{isize=isize ity, ea=ea, dst=RealReg d}, an)
1470 :     )
1471 :    
1472 :     and fexpr''(e as T.FREG(_,f)) =
1473 :     if isFMemReg f then transFexpr e else f
1474 :     | fexpr'' e = transFexpr e
1475 :    
1476 :     and transFexpr e =
1477 :     let val fd = newFreg() in doFexpr''(64, e, fd, []); fd end
1478 :    
1479 :     (*
1480 :     * Process a floating point operand. Put operand in register
1481 :     * when possible. The operand should match the given fty.
1482 :     *)
1483 :     and foperand(fty, e as T.FREG(fty', f)) =
1484 :     if fty = fty' then RealReg f else I.FPR(fexpr'' e)
1485 :     | foperand(fty, T.CVTF2F(_, _, e)) =
1486 :     foperand(fty, e) (* nop on the x86 *)
1487 :     | foperand(fty, e as T.FLOAD(fty', ea, mem)) =
1488 :     (* fold operand when the precison matches *)
1489 :     if fty = fty' then address(ea, mem) else I.FPR(fexpr'' e)
1490 :     | foperand(fty, e) = I.FPR(fexpr'' e)
1491 :    
1492 :     (*
1493 :     * Process a floating point operand.
1494 :     * Try to fold in a memory operand or conversion from an integer.
1495 :     *)
1496 :     and fioperand(T.FREG(fty,f)) = (REAL, fty, RealReg f, [])
1497 :     | fioperand(T.FLOAD(fty, ea, mem)) =
1498 :     (REAL, fty, address(ea, mem), [])
1499 :     | fioperand(T.CVTF2F(_, _, e)) = fioperand(e) (* nop on the x86 *)
1500 :     | fioperand(T.CVTI2F(_, ty, e)) = convertIntToFloat(ty, e)
1501 :     | fioperand(T.FMARK(e,an)) = fioperand(e) (* XXX *)
1502 :     | fioperand(e) = (REAL, 64, I.FPR(fexpr'' e), [])
1503 :    
1504 :     (* Generate binary operator. Since the real binary operators
1505 :     * does not take memory as destination, we also ensure this
1506 :     * does not happen.
1507 :     *)
1508 :     and fbinop(targetFty,
1509 :     binOp, binOpR, ibinOp, ibinOpR, lsrc, rsrc, fd, an) =
1510 :     (* Put the mem operand in rsrc *)
1511 :     let val _ = floatingPointUsed := true;
1512 :     fun isMemOpnd(T.FREG(_, f)) = isFMemReg f
1513 :     | isMemOpnd(T.FLOAD _) = true
1514 :     | isMemOpnd(T.CVTI2F(_, (16 | 32), _)) = true
1515 :     | isMemOpnd(T.CVTF2F(_, _, t)) = isMemOpnd t
1516 :     | isMemOpnd(T.FMARK(t, _)) = isMemOpnd t
1517 :     | isMemOpnd _ = false
1518 :     val (binOp, ibinOp, lsrc, rsrc) =
1519 :     if isMemOpnd lsrc then (binOpR, ibinOpR, rsrc, lsrc)
1520 :     else (binOp, ibinOp, lsrc, rsrc)
1521 :     val lsrc = foperand(targetFty, lsrc)
1522 :     val (kind, fty, rsrc, code) = fioperand(rsrc)
1523 :     fun dstMustBeFreg f =
1524 :     if targetFty <> 64 then
1525 :     let val tmpR = newFreg()
1526 :     val tmp = I.FPR tmpR
1527 :     in mark(f tmp, an);
1528 :     emit(I.FMOVE{fsize=fsize targetFty,
1529 :     src=tmp, dst=RealReg fd})
1530 :     end
1531 :     else mark(f(RealReg fd), an)
1532 :     in case kind of
1533 :     REAL =>
1534 :     dstMustBeFreg(fn dst =>
1535 :     I.FBINOP{fsize=fsize fty, binOp=binOp,
1536 :     lsrc=lsrc, rsrc=rsrc, dst=dst})
1537 :     | INTEGER =>
1538 :     (dstMustBeFreg(fn dst =>
1539 :     I.FIBINOP{isize=isize fty, binOp=ibinOp,
1540 :     lsrc=lsrc, rsrc=rsrc, dst=dst});
1541 :     emits code
1542 :     )
1543 :     end
1544 : george 545
1545 : leunga 731 and funop(fty, unOp, src, fd, an) =
1546 :     let val src = foperand(fty, src)
1547 :     in mark(I.FUNOP{fsize=fsize fty,
1548 :     unOp=unOp, src=src, dst=RealReg fd},an)
1549 :     end
1550 :    
1551 :     and doFexpr''(fty, e, fd, an) =
1552 :     case e of
1553 : george 889 T.FREG(_,fs) => if CB.sameColor(fs,fd) then ()
1554 : leunga 731 else fcopy''(fty, [fd], [fs], an)
1555 :     (* Stupid x86 does everything as 80-bits internally. *)
1556 :    
1557 :     (* Binary operators *)
1558 :     | T.FADD(_, a, b) => fbinop(fty,
1559 :     I.FADDL, I.FADDL, I.FIADDL, I.FIADDL,
1560 :     a, b, fd, an)
1561 :     | T.FSUB(_, a, b) => fbinop(fty,
1562 :     I.FSUBL, I.FSUBRL, I.FISUBL, I.FISUBRL,
1563 :     a, b, fd, an)
1564 :     | T.FMUL(_, a, b) => fbinop(fty,
1565 :     I.FMULL, I.FMULL, I.FIMULL, I.FIMULL,
1566 :     a, b, fd, an)
1567 :     | T.FDIV(_, a, b) => fbinop(fty,
1568 :     I.FDIVL, I.FDIVRL, I.FIDIVL, I.FIDIVRL,
1569 :     a, b, fd, an)
1570 :    
1571 :     (* Unary operators *)
1572 :     | T.FNEG(_, a) => funop(fty, I.FCHS, a, fd, an)
1573 :     | T.FABS(_, a) => funop(fty, I.FABS, a, fd, an)
1574 :     | T.FSQRT(_, a) => funop(fty, I.FSQRT, a, fd, an)
1575 :    
1576 :     (* Load *)
1577 :     | T.FLOAD(fty,ea,mem) => fload''(fty, ea, mem, fd, an)
1578 :    
1579 :     (* Type conversions *)
1580 :     | T.CVTF2F(_, _, e) => doFexpr''(fty, e, fd, an)
1581 :     | T.CVTI2F(_, ty, e) =>
1582 :     let val (_, ty, ea, cleanup) = convertIntToFloat(ty, e)
1583 :     in fiload''(ty, ea, fd, an);
1584 :     emits cleanup
1585 :     end
1586 :    
1587 :     | T.FMARK(e,A.MARKREG f) => (f fd; doFexpr''(fty, e, fd, an))
1588 :     | T.FMARK(e, a) => doFexpr''(fty, e, fd, a::an)
1589 :     | T.FPRED(e, c) => doFexpr''(fty, e, fd, A.CTRLUSE c::an)
1590 :     | T.FEXT fexp =>
1591 :     ExtensionComp.compileFext (reducer()) {e=fexp, fd=fd, an=an}
1592 :     | _ => error("doFexpr''")
1593 :    
1594 :     (*========================================================
1595 :     * Tie the two styles of fp code generation together
1596 :     *========================================================*)
1597 :     and fstore(fty, ea, d, mem, an) =
1598 :     if enableFastFPMode andalso !fast_floating_point
1599 :     then fstore''(fty, ea, d, mem, an)
1600 :     else fstore'(fty, ea, d, mem, an)
1601 :     and fload(fty, ea, d, mem, an) =
1602 :     if enableFastFPMode andalso !fast_floating_point
1603 :     then fload''(fty, ea, d, mem, an)
1604 :     else fload'(fty, ea, d, mem, an)
1605 :     and fexpr e =
1606 :     if enableFastFPMode andalso !fast_floating_point
1607 :     then fexpr'' e else fexpr' e
1608 :     and doFexpr(fty, e, fd, an) =
1609 :     if enableFastFPMode andalso !fast_floating_point
1610 :     then doFexpr''(fty, e, fd, an)
1611 :     else doFexpr'(fty, e, fd, an)
1612 :    
1613 : leunga 797 (*================================================================
1614 :     * Optimizations for x := x op y
1615 :     * Special optimizations:
1616 :     * Generate a binary operator, result must in memory.
1617 :     * The source must not be in memory
1618 :     *================================================================*)
1619 :     and binaryMem(binOp, src, dst, mem, an) =
1620 :     mark(I.BINARY{binOp=binOp, src=immedOrReg(operand src),
1621 :     dst=address(dst,mem)}, an)
1622 :     and unaryMem(unOp, opnd, mem, an) =
1623 :     mark(I.UNARY{unOp=unOp, opnd=address(opnd,mem)}, an)
1624 :    
1625 :     and isOne(T.LI n) = n = one
1626 :     | isOne _ = false
1627 :    
1628 :     (*
1629 :     * Perform optimizations based on recognizing
1630 :     * x := x op y or
1631 :     * x := y op x
1632 :     * first.
1633 :     *)
1634 :     and store(ty, ea, d, mem, an,
1635 :     {INC,DEC,ADD,SUB,NOT,NEG,SHL,SHR,SAR,OR,AND,XOR},
1636 :     doStore
1637 :     ) =
1638 :     let fun default() = doStore(ea, d, mem, an)
1639 :     fun binary1(t, t', unary, binary, ea', x) =
1640 :     if t = ty andalso t' = ty then
1641 :     if MLTreeUtils.eqRexp(ea, ea') then
1642 :     if isOne x then unaryMem(unary, ea, mem, an)
1643 :     else binaryMem(binary, x, ea, mem, an)
1644 :     else default()
1645 :     else default()
1646 :     fun unary(t,unOp, ea') =
1647 :     if t = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1648 :     unaryMem(unOp, ea, mem, an)
1649 :     else default()
1650 :     fun binary(t,t',binOp,ea',x) =
1651 :     if t = ty andalso t' = ty andalso
1652 :     MLTreeUtils.eqRexp(ea, ea') then
1653 :     binaryMem(binOp, x, ea, mem, an)
1654 :     else default()
1655 :    
1656 :     fun binaryCom1(t,unOp,binOp,x,y) =
1657 :     if t = ty then
1658 :     let fun again() =
1659 :     case y of
1660 :     T.LOAD(ty',ea',_) =>
1661 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1662 :     if isOne x then unaryMem(unOp, ea, mem, an)
1663 :     else binaryMem(binOp,x,ea,mem,an)
1664 :     else default()
1665 :     | _ => default()
1666 :     in case x of
1667 :     T.LOAD(ty',ea',_) =>
1668 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1669 :     if isOne y then unaryMem(unOp, ea, mem, an)
1670 :     else binaryMem(binOp,y,ea,mem,an)
1671 :     else again()
1672 :     | _ => again()
1673 :     end
1674 :     else default()
1675 :    
1676 :     fun binaryCom(t,binOp,x,y) =
1677 :     if t = ty then
1678 :     let fun again() =
1679 :     case y of
1680 :     T.LOAD(ty',ea',_) =>
1681 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1682 :     binaryMem(binOp,x,ea,mem,an)
1683 :     else default()
1684 :     | _ => default()
1685 :     in case x of
1686 :     T.LOAD(ty',ea',_) =>
1687 :     if ty' = ty andalso MLTreeUtils.eqRexp(ea, ea') then
1688 :     binaryMem(binOp,y,ea,mem,an)
1689 :     else again()
1690 :     | _ => again()
1691 :     end
1692 :     else default()
1693 :    
1694 :     in case d of
1695 :     T.ADD(t,x,y) => binaryCom1(t,INC,ADD,x,y)
1696 :     | T.SUB(t,T.LOAD(t',ea',_),x) => binary1(t,t',DEC,SUB,ea',x)
1697 :     | T.ORB(t,x,y) => binaryCom(t,OR,x,y)
1698 :     | T.ANDB(t,x,y) => binaryCom(t,AND,x,y)
1699 :     | T.XORB(t,x,y) => binaryCom(t,XOR,x,y)
1700 :     | T.SLL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHL,ea',x)
1701 :     | T.SRL(t,T.LOAD(t',ea',_),x) => binary(t,t',SHR,ea',x)
1702 :     | T.SRA(t,T.LOAD(t',ea',_),x) => binary(t,t',SAR,ea',x)
1703 :     | T.NEG(t,T.LOAD(t',ea',_)) => unary(t,NEG,ea')
1704 :     | T.NOTB(t,T.LOAD(t',ea',_)) => unary(t,NOT,ea')
1705 :     | _ => default()
1706 :     end (* store *)
1707 :    
1708 : george 545 (* generate code for a statement *)
1709 :     and stmt(T.MV(_, rd, e), an) = doExpr(e, rd, an)
1710 :     | stmt(T.FMV(fty, fd, e), an) = doFexpr(fty, e, fd, an)
1711 :     | stmt(T.CCMV(ccd, e), an) = doCCexpr(e, ccd, an)
1712 :     | stmt(T.COPY(_, dst, src), an) = copy(dst, src, an)
1713 :     | stmt(T.FCOPY(fty, dst, src), an) = fcopy(fty, dst, src, an)
1714 : leunga 744 | stmt(T.JMP(e, labs), an) = jmp(e, labs, an)
1715 : blume 839 | stmt(T.CALL{funct, targets, defs, uses, region, pops, ...}, an) =
1716 :     call(funct,targets,defs,uses,region,[],an, pops)
1717 :     | stmt(T.FLOW_TO(T.CALL{funct, targets, defs, uses, region, pops, ...},
1718 : leunga 796 cutTo), an) =
1719 : blume 839 call(funct,targets,defs,uses,region,cutTo,an, pops)
1720 : george 545 | stmt(T.RET _, an) = mark(I.RET NONE, an)
1721 : leunga 797 | stmt(T.STORE(8, ea, d, mem), an) =
1722 :     store(8, ea, d, mem, an, opcodes8, store8)
1723 :     | stmt(T.STORE(16, ea, d, mem), an) =
1724 :     store(16, ea, d, mem, an, opcodes16, store16)
1725 :     | stmt(T.STORE(32, ea, d, mem), an) =
1726 :     store(32, ea, d, mem, an, opcodes32, store32)
1727 :    
1728 : george 545 | stmt(T.FSTORE(fty, ea, d, mem), an) = fstore(fty, ea, d, mem, an)
1729 : leunga 744 | stmt(T.BCC(cc, lab), an) = branch(cc, lab, an)
1730 : george 545 | stmt(T.DEFINE l, _) = defineLabel l
1731 :     | stmt(T.ANNOTATION(s, a), an) = stmt(s, a::an)
1732 : george 555 | stmt(T.EXT s, an) =
1733 :     ExtensionComp.compileSext (reducer()) {stm=s, an=an}
1734 : george 545 | stmt(s, _) = doStmts(Gen.compileStm s)
1735 :    
1736 :     and doStmt s = stmt(s, [])
1737 :     and doStmts ss = app doStmt ss
1738 :    
1739 :     and beginCluster' _ =
1740 :     ((* Must be cleared by the client.
1741 :     * if rewriteMemReg then memRegsUsed := 0w0 else ();
1742 :     *)
1743 : leunga 731 floatingPointUsed := false;
1744 :     trapLabel := NONE;
1745 :     beginCluster 0
1746 :     )
1747 : george 545 and endCluster' a =
1748 : monnier 247 (case !trapLabel
1749 : monnier 411 of NONE => ()
1750 : george 545 | SOME(_, lab) => (defineLabel lab; emit(I.INTO))
1751 : monnier 411 (*esac*);
1752 : leunga 731 (* If floating point has been used allocate an extra
1753 :     * register just in case we didn't use any explicit register
1754 :     *)
1755 :     if !floatingPointUsed then (newFreg(); ())
1756 :     else ();
1757 : george 545 endCluster(a)
1758 :     )
1759 :    
1760 :     and reducer() =
1761 : george 984 TS.REDUCER{reduceRexp = expr,
1762 : george 545 reduceFexp = fexpr,
1763 :     reduceCCexp = ccExpr,
1764 :     reduceStm = stmt,
1765 :     operand = operand,
1766 :     reduceOperand = reduceOpnd,
1767 :     addressOf = fn e => address(e, I.Region.memory), (*XXX*)
1768 : george 1009 emit = mark',
1769 : george 545 instrStream = instrStream,
1770 :     mltreeStream = self()
1771 :     }
1772 :    
1773 :     and self() =
1774 : george 984 TS.S.STREAM
1775 : leunga 815 { beginCluster = beginCluster',
1776 :     endCluster = endCluster',
1777 :     emit = doStmt,
1778 :     pseudoOp = pseudoOp,
1779 :     defineLabel = defineLabel,
1780 :     entryLabel = entryLabel,
1781 :     comment = comment,
1782 :     annotation = annotation,
1783 :     getAnnotations = getAnnotations,
1784 :     exitBlock = fn mlrisc => exitBlock(cellset mlrisc)
1785 : george 545 }
1786 :    
1787 :     in self()
1788 : monnier 247 end
1789 :    
1790 : george 545 end (* functor *)
1791 :    
1792 :     end (* local *)

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